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Commit ae5ef9b2 authored by Ravikishore Pampana's avatar Ravikishore Pampana
Browse files

msm: camera: isp: Update bus width properly 



Do not read the hw register to update the bus width.
Update register with stored height and user space given width
Update the tfe core irq command register after clear the registers.

CRs-Fixed: 2545590
Change-Id: I3fd9e0ce4319cd19b94e9c83fa63aab37f26027e
Signed-off-by: default avatarRavikishore Pampana <rpampana@codeaurora.org>
parent 2eeb1a0b

drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c

+1 −1
Original line number Diff line number Diff line
@@ -1445,7 +1445,7 @@ static int cam_tfe_hw_mgr_acquire_res_tfe_csid_rdi( 
		csid_acquire.res_type = CAM_ISP_RESOURCE_PIX_PATH;

		csid_acquire.res_id = path_res_id;

		csid_acquire.in_port = in_port;

		csid_acquire.out_port = in_port->data;

		csid_acquire.out_port = out_port;

		csid_acquire.sync_mode = CAM_ISP_HW_SYNC_NONE;

		csid_acquire.node_res = NULL;

drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c

+9 −1
Original line number Diff line number Diff line
@@ -315,6 +315,10 @@ static int cam_tfe_csid_global_reset(struct cam_tfe_csid_hw *csid_hw) 
		rc = -ETIMEDOUT;

	}



	status = cam_io_r(soc_info->reg_map[0].mem_base +

		csid_reg->cmn_reg->csid_top_irq_status_addr);

	CAM_DBG(CAM_ISP, "Status reg %d", status);



	/* perform the SW registers reset */

	reinit_completion(&csid_hw->csid_top_complete);

	cam_io_w_mb(csid_reg->cmn_reg->csid_reg_rst_stb,
@@ -1834,12 +1838,16 @@ static int cam_tfe_csid_reset_retain_sw_reg( 
	if (rc < 0) {

		CAM_ERR(CAM_ISP, "CSID:%d csid_reset fail rc = %d",

			  csid_hw->hw_intf->hw_idx, rc);

		rc = -ETIMEDOUT;

		status = cam_io_r(soc_info->reg_map[0].mem_base +

			csid_reg->cmn_reg->csid_top_irq_status_addr);

		CAM_DBG(CAM_ISP, "Status reg %d", status);

		rc = 0;

	} else {

		CAM_DBG(CAM_ISP, "CSID:%d hw reset completed %d",

			csid_hw->hw_intf->hw_idx, rc);

		rc = 0;

	}



	cam_io_w_mb(1, soc_info->reg_map[0].mem_base +

		csid_reg->cmn_reg->csid_top_irq_clear_addr);

	cam_io_w_mb(1, soc_info->reg_map[0].mem_base +

drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_bus.c

+1 −5
Original line number Diff line number Diff line
@@ -1656,11 +1656,7 @@ static int cam_tfe_bus_update_wm(void *priv, void *cmd_args, 


		wm_data = tfe_out_data->wm_res[i]->res_priv;

		/* update width register */

		val = cam_io_r_mb(wm_data->common_data->mem_base +

			wm_data->hw_regs->image_cfg_0);

		/* mask previously written width but preserve height */

		val = val & 0xFFFF0000;

		val |= wm_data->width;

		val = ((wm_data->height << 16) | (wm_data->width & 0xFFFF));

		CAM_TFE_ADD_REG_VAL_PAIR(reg_val_pair, j,

			wm_data->hw_regs->image_cfg_0, val);

		CAM_DBG(CAM_ISP, "WM:%d image height and width 0x%x",

drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.c

+3 −3
Original line number Diff line number Diff line
@@ -710,6 +710,9 @@ irqreturn_t cam_tfe_irq(int irq_num, void *data) 
		cam_io_w(top_irq_status[i], mem_base +

			core_info->tfe_hw_info->top_irq_clear[i]);



	cam_io_w_mb(core_info->tfe_hw_info->global_clear_bitmask,

		mem_base + core_info->tfe_hw_info->top_irq_cmd);



	CAM_DBG(CAM_ISP, "TFE:%d IRQ status_0:0x%x status_1:0x%x status_2:0x%x",

		core_info->core_index, top_irq_status[0],

		top_irq_status[1], top_irq_status[2]);
@@ -738,9 +741,6 @@ irqreturn_t cam_tfe_irq(int irq_num, void *data) 
			bus_irq_status[1]);

	}



	cam_io_w_mb(core_info->tfe_hw_info->global_clear_bitmask,

		mem_base + core_info->tfe_hw_info->top_irq_cmd);



	/* check reset */

	if ((top_irq_status[0] & core_info->tfe_hw_info->reset_irq_mask[0]) ||

		(top_irq_status[1] &