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Commit ae4f0d46 authored by Joao Pinto's avatar Joao Pinto Committed by David S. Miller
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net: stmmac: rx/tx dma start/stop prepared for multiple queues 



This patch prepares the RX/TX DMA stop/start process for multiple queues.

Signed-off-by: default avatarJoao Pinto <jpinto@synopsys.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 4f513ecd

drivers/net/ethernet/stmicro/stmmac/common.h

+4 −4
Original line number Diff line number Diff line
@@ -433,10 +433,10 @@ struct stmmac_dma_ops { 
	void (*enable_dma_transmission) (void __iomem *ioaddr);

	void (*enable_dma_irq)(void __iomem *ioaddr, u32 chan);

	void (*disable_dma_irq)(void __iomem *ioaddr, u32 chan);

	void (*start_tx) (void __iomem *ioaddr);

	void (*stop_tx) (void __iomem *ioaddr);

	void (*start_rx) (void __iomem *ioaddr);

	void (*stop_rx) (void __iomem *ioaddr);

	void (*start_tx)(void __iomem *ioaddr, u32 chan);

	void (*stop_tx)(void __iomem *ioaddr, u32 chan);

	void (*start_rx)(void __iomem *ioaddr, u32 chan);

	void (*stop_rx)(void __iomem *ioaddr, u32 chan);

	int (*dma_interrupt) (void __iomem *ioaddr,

			      struct stmmac_extra_stats *x);

	/* If supported then get the optional core features */

drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h

+4 −4
Original line number Diff line number Diff line
@@ -188,10 +188,10 @@ void dwmac4_enable_dma_transmission(void __iomem *ioaddr, u32 tail_ptr); 
void dwmac4_enable_dma_irq(void __iomem *ioaddr, u32 chan);

void dwmac410_enable_dma_irq(void __iomem *ioaddr, u32 chan);

void dwmac4_disable_dma_irq(void __iomem *ioaddr, u32 chan);

void dwmac4_dma_start_tx(void __iomem *ioaddr);

void dwmac4_dma_stop_tx(void __iomem *ioaddr);

void dwmac4_dma_start_rx(void __iomem *ioaddr);

void dwmac4_dma_stop_rx(void __iomem *ioaddr);

void dwmac4_dma_start_tx(void __iomem *ioaddr, u32 chan);

void dwmac4_dma_stop_tx(void __iomem *ioaddr, u32 chan);

void dwmac4_dma_start_rx(void __iomem *ioaddr, u32 chan);

void dwmac4_dma_stop_rx(void __iomem *ioaddr, u32 chan);

int dwmac4_dma_interrupt(void __iomem *ioaddr,

			 struct stmmac_extra_stats *x);

void dwmac4_set_rx_ring_len(void __iomem *ioaddr, u32 len);

drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c

+12 −12
Original line number Diff line number Diff line
@@ -45,49 +45,49 @@ void dwmac4_set_tx_tail_ptr(void __iomem *ioaddr, u32 tail_ptr, u32 chan) 
	writel(tail_ptr, ioaddr + DMA_CHAN_TX_END_ADDR(0));

}



void dwmac4_dma_start_tx(void __iomem *ioaddr)

void dwmac4_dma_start_tx(void __iomem *ioaddr, u32 chan)

{

	u32 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(STMMAC_CHAN0));

	u32 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan));



	value |= DMA_CONTROL_ST;

	writel(value, ioaddr + DMA_CHAN_TX_CONTROL(STMMAC_CHAN0));

	writel(value, ioaddr + DMA_CHAN_TX_CONTROL(chan));



	value = readl(ioaddr + GMAC_CONFIG);

	value |= GMAC_CONFIG_TE;

	writel(value, ioaddr + GMAC_CONFIG);

}



void dwmac4_dma_stop_tx(void __iomem *ioaddr)

void dwmac4_dma_stop_tx(void __iomem *ioaddr, u32 chan)

{

	u32 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(STMMAC_CHAN0));

	u32 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan));



	value &= ~DMA_CONTROL_ST;

	writel(value, ioaddr + DMA_CHAN_TX_CONTROL(STMMAC_CHAN0));

	writel(value, ioaddr + DMA_CHAN_TX_CONTROL(chan));



	value = readl(ioaddr + GMAC_CONFIG);

	value &= ~GMAC_CONFIG_TE;

	writel(value, ioaddr + GMAC_CONFIG);

}



void dwmac4_dma_start_rx(void __iomem *ioaddr)

void dwmac4_dma_start_rx(void __iomem *ioaddr, u32 chan)

{

	u32 value = readl(ioaddr + DMA_CHAN_RX_CONTROL(STMMAC_CHAN0));

	u32 value = readl(ioaddr + DMA_CHAN_RX_CONTROL(chan));



	value |= DMA_CONTROL_SR;



	writel(value, ioaddr + DMA_CHAN_RX_CONTROL(STMMAC_CHAN0));

	writel(value, ioaddr + DMA_CHAN_RX_CONTROL(chan));



	value = readl(ioaddr + GMAC_CONFIG);

	value |= GMAC_CONFIG_RE;

	writel(value, ioaddr + GMAC_CONFIG);

}



void dwmac4_dma_stop_rx(void __iomem *ioaddr)

void dwmac4_dma_stop_rx(void __iomem *ioaddr, u32 chan)

{

	u32 value = readl(ioaddr + DMA_CHAN_RX_CONTROL(STMMAC_CHAN0));

	u32 value = readl(ioaddr + DMA_CHAN_RX_CONTROL(chan));



	value &= ~DMA_CONTROL_SR;

	writel(value, ioaddr + DMA_CHAN_RX_CONTROL(STMMAC_CHAN0));

	writel(value, ioaddr + DMA_CHAN_RX_CONTROL(chan));



	value = readl(ioaddr + GMAC_CONFIG);

	value &= ~GMAC_CONFIG_RE;

drivers/net/ethernet/stmicro/stmmac/dwmac_dma.h

+4 −4
Original line number Diff line number Diff line
@@ -139,10 +139,10 @@ 
void dwmac_enable_dma_transmission(void __iomem *ioaddr);

void dwmac_enable_dma_irq(void __iomem *ioaddr, u32 chan);

void dwmac_disable_dma_irq(void __iomem *ioaddr, u32 chan);

void dwmac_dma_start_tx(void __iomem *ioaddr);

void dwmac_dma_stop_tx(void __iomem *ioaddr);

void dwmac_dma_start_rx(void __iomem *ioaddr);

void dwmac_dma_stop_rx(void __iomem *ioaddr);

void dwmac_dma_start_tx(void __iomem *ioaddr, u32 chan);

void dwmac_dma_stop_tx(void __iomem *ioaddr, u32 chan);

void dwmac_dma_start_rx(void __iomem *ioaddr, u32 chan);

void dwmac_dma_stop_rx(void __iomem *ioaddr, u32 chan);

int dwmac_dma_interrupt(void __iomem *ioaddr, struct stmmac_extra_stats *x);

int dwmac_dma_reset(void __iomem *ioaddr);

drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c

+4 −4
Original line number Diff line number Diff line
@@ -57,28 +57,28 @@ void dwmac_disable_dma_irq(void __iomem *ioaddr, u32 chan) 
	writel(0, ioaddr + DMA_INTR_ENA);

}



void dwmac_dma_start_tx(void __iomem *ioaddr)

void dwmac_dma_start_tx(void __iomem *ioaddr, u32 chan)

{

	u32 value = readl(ioaddr + DMA_CONTROL);

	value |= DMA_CONTROL_ST;

	writel(value, ioaddr + DMA_CONTROL);

}



void dwmac_dma_stop_tx(void __iomem *ioaddr)

void dwmac_dma_stop_tx(void __iomem *ioaddr, u32 chan)

{

	u32 value = readl(ioaddr + DMA_CONTROL);

	value &= ~DMA_CONTROL_ST;

	writel(value, ioaddr + DMA_CONTROL);

}



void dwmac_dma_start_rx(void __iomem *ioaddr)

void dwmac_dma_start_rx(void __iomem *ioaddr, u32 chan)

{

	u32 value = readl(ioaddr + DMA_CONTROL);

	value |= DMA_CONTROL_SR;

	writel(value, ioaddr + DMA_CONTROL);

}



void dwmac_dma_stop_rx(void __iomem *ioaddr)

void dwmac_dma_stop_rx(void __iomem *ioaddr, u32 chan)

{

	u32 value = readl(ioaddr + DMA_CONTROL);

	value &= ~DMA_CONTROL_SR;