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Commit adec9bc3 authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/nouveau/pwr: tidy 



Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 3d50d4dc

drivers/gpu/drm/nouveau/core/engine/device/gm100.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -78,7 +78,7 @@ gm100_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;

		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;

		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;

		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;

#if 0

#if 0

		device->oclass[NVDEV_SUBDEV_PWR    ] = &nv108_pwr_oclass;

		device->oclass[NVDEV_SUBDEV_PWR    ] =  nv108_pwr_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;

#endif

#endif

		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;

drivers/gpu/drm/nouveau/core/engine/device/nv50.c

+4 −4
Original line number Original line Diff line number Diff line
@@ -350,7 +350,7 @@ nv50_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;

		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;

		device->oclass[NVDEV_SUBDEV_VM     ] = &nv50_vmmgr_oclass;

		device->oclass[NVDEV_SUBDEV_VM     ] = &nv50_vmmgr_oclass;

		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;

		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;

		device->oclass[NVDEV_SUBDEV_PWR    ] = &nva3_pwr_oclass;

		device->oclass[NVDEV_SUBDEV_PWR    ] =  nva3_pwr_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;

		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;
@@ -380,7 +380,7 @@ nv50_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;

		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;

		device->oclass[NVDEV_SUBDEV_VM     ] = &nv50_vmmgr_oclass;

		device->oclass[NVDEV_SUBDEV_VM     ] = &nv50_vmmgr_oclass;

		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;

		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;

		device->oclass[NVDEV_SUBDEV_PWR    ] = &nva3_pwr_oclass;

		device->oclass[NVDEV_SUBDEV_PWR    ] =  nva3_pwr_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;

		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;
@@ -409,7 +409,7 @@ nv50_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;

		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;

		device->oclass[NVDEV_SUBDEV_VM     ] = &nv50_vmmgr_oclass;

		device->oclass[NVDEV_SUBDEV_VM     ] = &nv50_vmmgr_oclass;

		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;

		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;

		device->oclass[NVDEV_SUBDEV_PWR    ] = &nva3_pwr_oclass;

		device->oclass[NVDEV_SUBDEV_PWR    ] =  nva3_pwr_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;

		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;
@@ -438,7 +438,7 @@ nv50_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;

		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;

		device->oclass[NVDEV_SUBDEV_VM     ] = &nv50_vmmgr_oclass;

		device->oclass[NVDEV_SUBDEV_VM     ] = &nv50_vmmgr_oclass;

		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;

		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;

		device->oclass[NVDEV_SUBDEV_PWR    ] = &nva3_pwr_oclass;

		device->oclass[NVDEV_SUBDEV_PWR    ] =  nva3_pwr_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;

		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;

drivers/gpu/drm/nouveau/core/engine/device/nvc0.c

+8 −8
Original line number Original line Diff line number Diff line
@@ -75,7 +75,7 @@ nvc0_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;

		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;

		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;

		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;

		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;

		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;

		device->oclass[NVDEV_SUBDEV_PWR    ] = &nvc0_pwr_oclass;

		device->oclass[NVDEV_SUBDEV_PWR    ] =  nvc0_pwr_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;

		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  nvc0_fifo_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  nvc0_fifo_oclass;
@@ -107,7 +107,7 @@ nvc0_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;

		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;

		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;

		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;

		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;

		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;

		device->oclass[NVDEV_SUBDEV_PWR    ] = &nvc0_pwr_oclass;

		device->oclass[NVDEV_SUBDEV_PWR    ] =  nvc0_pwr_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;

		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  nvc0_fifo_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  nvc0_fifo_oclass;
@@ -139,7 +139,7 @@ nvc0_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;

		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;

		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;

		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;

		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;

		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;

		device->oclass[NVDEV_SUBDEV_PWR    ] = &nvc0_pwr_oclass;

		device->oclass[NVDEV_SUBDEV_PWR    ] =  nvc0_pwr_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;

		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  nvc0_fifo_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  nvc0_fifo_oclass;
@@ -170,7 +170,7 @@ nvc0_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;

		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;

		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;

		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;

		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;

		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;

		device->oclass[NVDEV_SUBDEV_PWR    ] = &nvc0_pwr_oclass;

		device->oclass[NVDEV_SUBDEV_PWR    ] =  nvc0_pwr_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;

		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  nvc0_fifo_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  nvc0_fifo_oclass;
@@ -202,7 +202,7 @@ nvc0_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;

		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;

		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;

		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;

		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;

		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;

		device->oclass[NVDEV_SUBDEV_PWR    ] = &nvc0_pwr_oclass;

		device->oclass[NVDEV_SUBDEV_PWR    ] =  nvc0_pwr_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;

		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  nvc0_fifo_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  nvc0_fifo_oclass;
@@ -234,7 +234,7 @@ nvc0_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;

		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;

		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;

		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;

		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;

		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;

		device->oclass[NVDEV_SUBDEV_PWR    ] = &nvc0_pwr_oclass;

		device->oclass[NVDEV_SUBDEV_PWR    ] =  nvc0_pwr_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;

		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  nvc0_fifo_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  nvc0_fifo_oclass;
@@ -265,7 +265,7 @@ nvc0_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;

		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;

		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;

		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;

		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;

		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;

		device->oclass[NVDEV_SUBDEV_PWR    ] = &nvc0_pwr_oclass;

		device->oclass[NVDEV_SUBDEV_PWR    ] =  nvc0_pwr_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;

		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  nvc0_fifo_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  nvc0_fifo_oclass;
@@ -297,7 +297,7 @@ nvc0_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;

		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;

		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;

		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;

		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;

		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;

		device->oclass[NVDEV_SUBDEV_PWR    ] = &nvd0_pwr_oclass;

		device->oclass[NVDEV_SUBDEV_PWR    ] =  nvd0_pwr_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;

		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  nvc0_fifo_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  nvc0_fifo_oclass;

drivers/gpu/drm/nouveau/core/engine/device/nve0.c

+6 −6
Original line number Original line Diff line number Diff line
@@ -75,7 +75,7 @@ nve0_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;

		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;

		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;

		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;

		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;

		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;

		device->oclass[NVDEV_SUBDEV_PWR    ] = &nvd0_pwr_oclass;

		device->oclass[NVDEV_SUBDEV_PWR    ] =  nvd0_pwr_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;

		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  nve0_fifo_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  nve0_fifo_oclass;
@@ -108,7 +108,7 @@ nve0_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;

		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;

		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;

		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;

		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;

		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;

		device->oclass[NVDEV_SUBDEV_PWR    ] = &nvd0_pwr_oclass;

		device->oclass[NVDEV_SUBDEV_PWR    ] =  nvd0_pwr_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;

		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  nve0_fifo_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  nve0_fifo_oclass;
@@ -141,7 +141,7 @@ nve0_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;

		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;

		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;

		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;

		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;

		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;

		device->oclass[NVDEV_SUBDEV_PWR    ] = &nvd0_pwr_oclass;

		device->oclass[NVDEV_SUBDEV_PWR    ] =  nvd0_pwr_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;

		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  nve0_fifo_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  nve0_fifo_oclass;
@@ -191,7 +191,7 @@ nve0_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;

		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;

		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;

		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;

		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;

		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;

		device->oclass[NVDEV_SUBDEV_PWR    ] = &nvd0_pwr_oclass;

		device->oclass[NVDEV_SUBDEV_PWR    ] =  nvd0_pwr_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;

		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  nve0_fifo_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  nve0_fifo_oclass;
@@ -224,7 +224,7 @@ nve0_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;

		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;

		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;

		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;

		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;

		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;

		device->oclass[NVDEV_SUBDEV_PWR    ] = &nvd0_pwr_oclass;

		device->oclass[NVDEV_SUBDEV_PWR    ] =  nvd0_pwr_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;

		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  nve0_fifo_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  nve0_fifo_oclass;
@@ -257,7 +257,7 @@ nve0_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;

		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;

		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;

		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;

		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;

		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;

		device->oclass[NVDEV_SUBDEV_PWR    ] = &nv108_pwr_oclass;

		device->oclass[NVDEV_SUBDEV_PWR    ] =  nv108_pwr_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;

		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv108_fifo_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv108_fifo_oclass;

drivers/gpu/drm/nouveau/core/include/subdev/pwr.h

+4 −35
Original line number Original line Diff line number Diff line
@@ -7,18 +7,6 @@ 
struct nouveau_pwr {

struct nouveau_pwr {

	struct nouveau_subdev base;

	struct nouveau_subdev base;





	struct {

		u32 limit;

		u32 *data;

		u32  size;

	} code;



	struct {

		u32 limit;

		u32 *data;

		u32  size;

	} data;



	struct {

	struct {

		u32 base;

		u32 base;

		u32 size;

		u32 size;
@@ -44,29 +32,10 @@ nouveau_pwr(void *obj) 
	return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_PWR];

	return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_PWR];

}

}





#define nouveau_pwr_create(p, e, o, d)                                         \

extern struct nouveau_oclass *nva3_pwr_oclass;

	nouveau_pwr_create_((p), (e), (o), sizeof(**d), (void **)d)

extern struct nouveau_oclass *nvc0_pwr_oclass;

#define nouveau_pwr_destroy(p)                                                 \

extern struct nouveau_oclass *nvd0_pwr_oclass;

	nouveau_subdev_destroy(&(p)->base)

extern struct nouveau_oclass *nv108_pwr_oclass;

#define nouveau_pwr_init(p) ({                                                 \

	struct nouveau_pwr *ppwr = (p);                                        \

	_nouveau_pwr_init(nv_object(ppwr));                                    \

})

#define nouveau_pwr_fini(p,s) ({                                               \

	struct nouveau_pwr *ppwr = (p);                                        \

	_nouveau_pwr_fini(nv_object(ppwr), (s));                               \

})



int nouveau_pwr_create_(struct nouveau_object *, struct nouveau_object *,

			   struct nouveau_oclass *, int, void **);

#define _nouveau_pwr_dtor _nouveau_subdev_dtor

int _nouveau_pwr_init(struct nouveau_object *);

int _nouveau_pwr_fini(struct nouveau_object *, bool);



extern struct nouveau_oclass nva3_pwr_oclass;

extern struct nouveau_oclass nvc0_pwr_oclass;

extern struct nouveau_oclass nvd0_pwr_oclass;

extern struct nouveau_oclass nv108_pwr_oclass;





/* interface to MEMX process running on PPWR */

/* interface to MEMX process running on PPWR */

struct nouveau_memx;

struct nouveau_memx;