Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit adac5d53 authored by Paul Burton's avatar Paul Burton Committed by Ralf Baechle
Browse files

MIPS: detect presence of the FRE & UFR bits 



Detect the presence of the Config5 FRE & UFE bits, as indicated by the
FREP bit in FPIR. Record this as a CPU option bit, and provide a
cpu_has_fre macro to ease checking of that option bit.

Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: Alexander Viro <viro@zeniv.linux.org.uk>
Cc: linux-fsdevel@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/7678/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 5ff04a84

arch/mips/include/asm/cpu-features.h

+4 −0
Original line number Original line Diff line number Diff line
@@ -344,4 +344,8 @@ 
# define cpu_has_msa		0

# define cpu_has_msa		0

#endif

#endif





#ifndef cpu_has_fre

# define cpu_has_fre		(cpu_data[0].options & MIPS_CPU_FRE)

#endif



#endif /* __ASM_CPU_FEATURES_H */
 
#endif /* __ASM_CPU_FEATURES_H */

arch/mips/include/asm/cpu.h

+1 −0
Original line number Original line Diff line number Diff line
@@ -368,6 +368,7 @@ enum cpu_type_enum { 
#define MIPS_CPU_HTW		0x100000000ull /* CPU support Hardware Page Table Walker */

#define MIPS_CPU_HTW		0x100000000ull /* CPU support Hardware Page Table Walker */

#define MIPS_CPU_RIXIEX		0x200000000ull /* CPU has unique exception codes for {Read, Execute}-Inhibit exceptions */

#define MIPS_CPU_RIXIEX		0x200000000ull /* CPU has unique exception codes for {Read, Execute}-Inhibit exceptions */

#define MIPS_CPU_MAAR		0x400000000ull /* MAAR(I) registers are present */

#define MIPS_CPU_MAAR		0x400000000ull /* MAAR(I) registers are present */

#define MIPS_CPU_FRE		0x800000000ull /* FRE & UFE bits implemented */





/*

/*

 * CPU ASE encodings

 * CPU ASE encodings

arch/mips/kernel/cpu-probe.c

+2 −0
Original line number Original line Diff line number Diff line
@@ -1317,6 +1317,8 @@ void cpu_probe(void) 
				    MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)) {

				    MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)) {

			if (c->fpu_id & MIPS_FPIR_3D)

			if (c->fpu_id & MIPS_FPIR_3D)

				c->ases |= MIPS_ASE_MIPS3D;

				c->ases |= MIPS_ASE_MIPS3D;

			if (c->fpu_id & MIPS_FPIR_FREP)

				c->options |= MIPS_CPU_FRE;

		}

		}

	}

	}