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Commit ada6770e authored by Rex Zhu's avatar Rex Zhu Committed by Alex Deucher
Browse files

drm/amd/pp: Remove cgs_query_system_info 



Get gpu info through adev directly in powerplay

Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarRex Zhu <Rex.Zhu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 6848d73e

drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c

+0 −59
Original line number Diff line number Diff line
@@ -835,64 +835,6 @@ static int amdgpu_cgs_is_virtualization_enabled(void *cgs_device) 
	return amdgpu_sriov_vf(adev);

}



static int amdgpu_cgs_query_system_info(struct cgs_device *cgs_device,

					struct cgs_system_info *sys_info)

{

	CGS_FUNC_ADEV;



	if (NULL == sys_info)

		return -ENODEV;



	if (sizeof(struct cgs_system_info) != sys_info->size)

		return -ENODEV;



	switch (sys_info->info_id) {

	case CGS_SYSTEM_INFO_ADAPTER_BDF_ID:

		sys_info->value = adev->pdev->devfn | (adev->pdev->bus->number << 8);

		break;

	case CGS_SYSTEM_INFO_PCIE_GEN_INFO:

		sys_info->value = adev->pm.pcie_gen_mask;

		break;

	case CGS_SYSTEM_INFO_PCIE_MLW:

		sys_info->value = adev->pm.pcie_mlw_mask;

		break;

	case CGS_SYSTEM_INFO_PCIE_DEV:

		sys_info->value = adev->pdev->device;

		break;

	case CGS_SYSTEM_INFO_PCIE_REV:

		sys_info->value = adev->pdev->revision;

		break;

	case CGS_SYSTEM_INFO_CG_FLAGS:

		sys_info->value = adev->cg_flags;

		break;

	case CGS_SYSTEM_INFO_PG_FLAGS:

		sys_info->value = adev->pg_flags;

		break;

	case CGS_SYSTEM_INFO_GFX_CU_INFO:

		sys_info->value = adev->gfx.cu_info.number;

		break;

	case CGS_SYSTEM_INFO_GFX_SE_INFO:

		sys_info->value = adev->gfx.config.max_shader_engines;

		break;

	case CGS_SYSTEM_INFO_PCIE_SUB_SYS_ID:

		sys_info->value = adev->pdev->subsystem_device;

		break;

	case CGS_SYSTEM_INFO_PCIE_SUB_SYS_VENDOR_ID:

		sys_info->value = adev->pdev->subsystem_vendor;

		break;

	case CGS_SYSTEM_INFO_PCIE_BUS_DEVFN:

		sys_info->value = adev->pdev->devfn;

		break;

	case CGS_SYSTEM_INFO_VRAM_WIDTH:

		sys_info->value = adev->gmc.vram_width;

		break;

	default:

		return -ENODEV;

	}



	return 0;

}



static int amdgpu_cgs_get_active_displays_info(struct cgs_device *cgs_device,

					  struct cgs_display_info *info)

{
@@ -996,7 +938,6 @@ static const struct cgs_ops amdgpu_cgs_ops = { 
	.set_clockgating_state = amdgpu_cgs_set_clockgating_state,

	.get_active_displays_info = amdgpu_cgs_get_active_displays_info,

	.notify_dpm_enabled = amdgpu_cgs_notify_dpm_enabled,

	.query_system_info = amdgpu_cgs_query_system_info,

	.is_virtualization_enabled = amdgpu_cgs_is_virtualization_enabled,

	.enter_safe_mode = amdgpu_cgs_enter_safe_mode,

	.lock_grbm_idx = amdgpu_cgs_lock_grbm_idx,

drivers/gpu/drm/amd/include/cgs_common.h

+0 −34
Original line number Diff line number Diff line
@@ -88,33 +88,6 @@ enum cgs_ucode_id { 
	CGS_UCODE_ID_MAXIMUM,

};



enum cgs_system_info_id {

	CGS_SYSTEM_INFO_ADAPTER_BDF_ID = 1,

	CGS_SYSTEM_INFO_PCIE_GEN_INFO,

	CGS_SYSTEM_INFO_PCIE_MLW,

	CGS_SYSTEM_INFO_PCIE_DEV,

	CGS_SYSTEM_INFO_PCIE_REV,

	CGS_SYSTEM_INFO_CG_FLAGS,

	CGS_SYSTEM_INFO_PG_FLAGS,

	CGS_SYSTEM_INFO_GFX_CU_INFO,

	CGS_SYSTEM_INFO_GFX_SE_INFO,

	CGS_SYSTEM_INFO_PCIE_SUB_SYS_ID,

	CGS_SYSTEM_INFO_PCIE_SUB_SYS_VENDOR_ID,

	CGS_SYSTEM_INFO_PCIE_BUS_DEVFN,

	CGS_SYSTEM_INFO_VRAM_WIDTH,

	CGS_SYSTEM_INFO_ID_MAXIMUM,

};



struct cgs_system_info {

	uint64_t			size;

	enum cgs_system_info_id		info_id;

	union {

		void			*ptr;

		uint64_t		value;

	};

	uint64_t			padding[13];

};



/*

 * enum cgs_resource_type - GPU resource type

 */
@@ -375,9 +348,6 @@ typedef int(*cgs_get_active_displays_info)( 


typedef int (*cgs_notify_dpm_enabled)(struct cgs_device *cgs_device, bool enabled);



typedef int (*cgs_query_system_info)(struct cgs_device *cgs_device,

				struct cgs_system_info *sys_info);



typedef int (*cgs_is_virtualization_enabled_t)(void *cgs_device);



typedef int (*cgs_enter_safe_mode)(struct cgs_device *cgs_device, bool en);
@@ -416,8 +386,6 @@ struct cgs_ops { 
	cgs_get_active_displays_info get_active_displays_info;

	/* notify dpm enabled */

	cgs_notify_dpm_enabled notify_dpm_enabled;

	/* get system info */

	cgs_query_system_info query_system_info;

	cgs_is_virtualization_enabled_t is_virtualization_enabled;

	cgs_enter_safe_mode enter_safe_mode;

	cgs_lock_grbm_idx lock_grbm_idx;
@@ -483,8 +451,6 @@ struct cgs_device 
#define cgs_get_active_displays_info(dev, info)	\

	CGS_CALL(get_active_displays_info, dev, info)



#define cgs_query_system_info(dev, sys_info)	\

	CGS_CALL(query_system_info, dev, sys_info)

#define cgs_get_pci_resource(cgs_device, resource_type, size, offset, \

	resource_base) \

	CGS_CALL(get_pci_resource, cgs_device, resource_type, size, offset, \

drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c

+9 −13
Original line number Diff line number Diff line
@@ -173,8 +173,7 @@ static uint32_t cz_get_max_sclk_level(struct pp_hwmgr *hwmgr) 
static int cz_initialize_dpm_defaults(struct pp_hwmgr *hwmgr)

{

	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);

	struct cgs_system_info sys_info = {0};

	int result;

	struct amdgpu_device *adev = hwmgr->adev;



	cz_hwmgr->gfx_ramp_step = 256*25/100;

	cz_hwmgr->gfx_ramp_delay = 1; /* by default, we delay 1us */
@@ -234,17 +233,14 @@ static int cz_initialize_dpm_defaults(struct pp_hwmgr *hwmgr) 
		      PHM_PlatformCaps_UVDPowerGating);

	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,

		      PHM_PlatformCaps_VCEPowerGating);

	sys_info.size = sizeof(struct cgs_system_info);

	sys_info.info_id = CGS_SYSTEM_INFO_PG_FLAGS;

	result = cgs_query_system_info(hwmgr->device, &sys_info);

	if (!result) {

		if (sys_info.value & AMD_PG_SUPPORT_UVD)



	if (adev->pg_flags & AMD_PG_SUPPORT_UVD)

		phm_cap_set(hwmgr->platform_descriptor.platformCaps,

			      PHM_PlatformCaps_UVDPowerGating);

		if (sys_info.value & AMD_PG_SUPPORT_VCE)

	if (adev->pg_flags & AMD_PG_SUPPORT_VCE)

		phm_cap_set(hwmgr->platform_descriptor.platformCaps,

			      PHM_PlatformCaps_VCEPowerGating);

	}





	return 0;

}

drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c

+15 −39
Original line number Diff line number Diff line
@@ -64,30 +64,16 @@ uint16_t convert_to_vddc(uint8_t vid) 
	return (uint16_t) ((6200 - (vid * 25)) / VOLTAGE_SCALE);

}



static int phm_get_pci_bus_devfn(struct pp_hwmgr *hwmgr,

		struct cgs_system_info *sys_info)

{

	sys_info->size = sizeof(struct cgs_system_info);

	sys_info->info_id = CGS_SYSTEM_INFO_PCIE_BUS_DEVFN;



	return cgs_query_system_info(hwmgr->device, sys_info);

}



static int phm_thermal_l2h_irq(void *private_data,

		 unsigned src_id, const uint32_t *iv_entry)

{

	struct pp_hwmgr *hwmgr = (struct pp_hwmgr *)private_data;

	struct cgs_system_info sys_info = {0};

	int result;



	result = phm_get_pci_bus_devfn(hwmgr, &sys_info);

	if (result)

		return -EINVAL;

	struct amdgpu_device *adev = hwmgr->adev;



	pr_warn("GPU over temperature range detected on PCIe %lld:%lld.%lld!\n",

			PCI_BUS_NUM(sys_info.value),

			PCI_SLOT(sys_info.value),

			PCI_FUNC(sys_info.value));

	pr_warn("GPU over temperature range detected on PCIe %d:%d.%d!\n",

			PCI_BUS_NUM(adev->pdev->devfn),

			PCI_SLOT(adev->pdev->devfn),

			PCI_FUNC(adev->pdev->devfn));

	return 0;

}
@@ -95,17 +81,12 @@ static int phm_thermal_h2l_irq(void *private_data, 
		 unsigned src_id, const uint32_t *iv_entry)

{

	struct pp_hwmgr *hwmgr = (struct pp_hwmgr *)private_data;

	struct cgs_system_info sys_info = {0};

	int result;



	result = phm_get_pci_bus_devfn(hwmgr, &sys_info);

	if (result)

		return -EINVAL;

	struct amdgpu_device *adev = hwmgr->adev;



	pr_warn("GPU under temperature range detected on PCIe %lld:%lld.%lld!\n",

			PCI_BUS_NUM(sys_info.value),

			PCI_SLOT(sys_info.value),

			PCI_FUNC(sys_info.value));

	pr_warn("GPU under temperature range detected on PCIe %d:%d.%d!\n",

			PCI_BUS_NUM(adev->pdev->devfn),

			PCI_SLOT(adev->pdev->devfn),

			PCI_FUNC(adev->pdev->devfn));

	return 0;

}
@@ -113,17 +94,12 @@ static int phm_ctf_irq(void *private_data, 
		 unsigned src_id, const uint32_t *iv_entry)

{

	struct pp_hwmgr *hwmgr = (struct pp_hwmgr *)private_data;

	struct cgs_system_info sys_info = {0};

	int result;



	result = phm_get_pci_bus_devfn(hwmgr, &sys_info);

	if (result)

		return -EINVAL;

	struct amdgpu_device *adev = hwmgr->adev;



	pr_warn("GPU Critical Temperature Fault detected on PCIe %lld:%lld.%lld!\n",

			PCI_BUS_NUM(sys_info.value),

			PCI_SLOT(sys_info.value),

			PCI_FUNC(sys_info.value));

	pr_warn("GPU Critical Temperature Fault detected on PCIe %d:%d.%d!\n",

			PCI_BUS_NUM(adev->pdev->devfn),

			PCI_SLOT(adev->pdev->devfn),

			PCI_FUNC(adev->pdev->devfn));

	return 0;

}

drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c

+3 −14
Original line number Diff line number Diff line
@@ -472,23 +472,12 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr, 
 */

int smu7_enable_per_cu_power_gating(struct pp_hwmgr *hwmgr, bool enable)

{

	struct cgs_system_info sys_info = {0};

	uint32_t active_cus;

	int result;



	sys_info.size = sizeof(struct cgs_system_info);

	sys_info.info_id = CGS_SYSTEM_INFO_GFX_CU_INFO;



	result = cgs_query_system_info(hwmgr->device, &sys_info);



	if (result)

		return -EINVAL;



	active_cus = sys_info.value;

	struct amdgpu_device *adev = hwmgr->adev;



	if (enable)

		return smum_send_msg_to_smc_with_parameter(hwmgr,

				PPSMC_MSG_GFX_CU_PG_ENABLE, active_cus);

					PPSMC_MSG_GFX_CU_PG_ENABLE,

					adev->gfx.cu_info.number);

	else

		return smum_send_msg_to_smc(hwmgr,

				PPSMC_MSG_GFX_CU_PG_DISABLE);