Loading arch/arm64/boot/dts/qcom/kona-sde.dtsi +2 −2 Original line number Diff line number Diff line Loading @@ -176,8 +176,8 @@ qcom,sde-vig-csc-off = <0x1a00>; qcom,sde-vig-qseed-off = <0xa00>; qcom,sde-vig-qseed-size = <0xa0>; qcom,sde-vig-gamut = <0x1d00 0x00050000>; qcom,sde-vig-igc = <0x1d00 0x00050000>; qcom,sde-vig-gamut = <0x1d00 0x00060000>; qcom,sde-vig-igc = <0x1d00 0x00060000>; qcom,sde-vig-inverse-pma; }; Loading drivers/gpu/drm/msm/sde/sde_hw_reg_dma_v1_color_proc.c +6 −0 Original line number Diff line number Diff line Loading @@ -1758,6 +1758,7 @@ void reg_dmav1_setup_vig_gamutv5(struct sde_hw_pipe *ctx, void *cfg) if (!hw_cfg->payload) { DRM_DEBUG_DRIVER("disable gamut feature\n"); /* v5 and v6 call the same off version */ vig_gamutv5_off(ctx, cfg); return; } Loading Loading @@ -1849,6 +1850,11 @@ void reg_dmav1_setup_vig_gamutv5(struct sde_hw_pipe *ctx, void *cfg) DRM_ERROR("failed to kick off ret %d\n", rc); } void reg_dmav1_setup_vig_gamutv6(struct sde_hw_pipe *ctx, void *cfg) { reg_dmav1_setup_vig_gamutv5(ctx, cfg); } static void vig_igcv5_off(struct sde_hw_pipe *ctx, void *cfg) { int rc; Loading drivers/gpu/drm/msm/sde/sde_hw_reg_dma_v1_color_proc.h +8 −0 Original line number Diff line number Diff line Loading @@ -127,6 +127,14 @@ int reg_dmav1_init_sspp_op_v4(int feature, enum sde_sspp idx); */ void reg_dmav1_setup_vig_gamutv5(struct sde_hw_pipe *ctx, void *cfg); /** * reg_dmav1_setup_vig_gamutv6() - VIG 3D lut gamut v6 implementation * using reg dma v1. * @ctx: sspp ctx info * @cfg: pointer to struct sde_hw_cp_cfg */ void reg_dmav1_setup_vig_gamutv6(struct sde_hw_pipe *ctx, void *cfg); /** * reg_dmav1_setup_vig_igcv5() - VIG 1D lut IGC v5 implementation * using reg dma v1. Loading drivers/gpu/drm/msm/sde/sde_hw_sspp.c +11 −0 Original line number Diff line number Diff line Loading @@ -1014,6 +1014,17 @@ static void _setup_layer_ops_colorproc(struct sde_hw_pipe *c, else c->ops.setup_vig_gamut = NULL; } if (c->cap->sblk->gamut_blk.version == (SDE_COLOR_PROCESS_VER(0x6, 0x0))) { ret = reg_dmav1_init_sspp_op_v4(SDE_SSPP_VIG_GAMUT, c->idx); if (!ret) c->ops.setup_vig_gamut = reg_dmav1_setup_vig_gamutv6; else c->ops.setup_vig_gamut = NULL; } } if (test_bit(SDE_SSPP_VIG_IGC, &features)) { Loading Loading
arch/arm64/boot/dts/qcom/kona-sde.dtsi +2 −2 Original line number Diff line number Diff line Loading @@ -176,8 +176,8 @@ qcom,sde-vig-csc-off = <0x1a00>; qcom,sde-vig-qseed-off = <0xa00>; qcom,sde-vig-qseed-size = <0xa0>; qcom,sde-vig-gamut = <0x1d00 0x00050000>; qcom,sde-vig-igc = <0x1d00 0x00050000>; qcom,sde-vig-gamut = <0x1d00 0x00060000>; qcom,sde-vig-igc = <0x1d00 0x00060000>; qcom,sde-vig-inverse-pma; }; Loading
drivers/gpu/drm/msm/sde/sde_hw_reg_dma_v1_color_proc.c +6 −0 Original line number Diff line number Diff line Loading @@ -1758,6 +1758,7 @@ void reg_dmav1_setup_vig_gamutv5(struct sde_hw_pipe *ctx, void *cfg) if (!hw_cfg->payload) { DRM_DEBUG_DRIVER("disable gamut feature\n"); /* v5 and v6 call the same off version */ vig_gamutv5_off(ctx, cfg); return; } Loading Loading @@ -1849,6 +1850,11 @@ void reg_dmav1_setup_vig_gamutv5(struct sde_hw_pipe *ctx, void *cfg) DRM_ERROR("failed to kick off ret %d\n", rc); } void reg_dmav1_setup_vig_gamutv6(struct sde_hw_pipe *ctx, void *cfg) { reg_dmav1_setup_vig_gamutv5(ctx, cfg); } static void vig_igcv5_off(struct sde_hw_pipe *ctx, void *cfg) { int rc; Loading
drivers/gpu/drm/msm/sde/sde_hw_reg_dma_v1_color_proc.h +8 −0 Original line number Diff line number Diff line Loading @@ -127,6 +127,14 @@ int reg_dmav1_init_sspp_op_v4(int feature, enum sde_sspp idx); */ void reg_dmav1_setup_vig_gamutv5(struct sde_hw_pipe *ctx, void *cfg); /** * reg_dmav1_setup_vig_gamutv6() - VIG 3D lut gamut v6 implementation * using reg dma v1. * @ctx: sspp ctx info * @cfg: pointer to struct sde_hw_cp_cfg */ void reg_dmav1_setup_vig_gamutv6(struct sde_hw_pipe *ctx, void *cfg); /** * reg_dmav1_setup_vig_igcv5() - VIG 1D lut IGC v5 implementation * using reg dma v1. Loading
drivers/gpu/drm/msm/sde/sde_hw_sspp.c +11 −0 Original line number Diff line number Diff line Loading @@ -1014,6 +1014,17 @@ static void _setup_layer_ops_colorproc(struct sde_hw_pipe *c, else c->ops.setup_vig_gamut = NULL; } if (c->cap->sblk->gamut_blk.version == (SDE_COLOR_PROCESS_VER(0x6, 0x0))) { ret = reg_dmav1_init_sspp_op_v4(SDE_SSPP_VIG_GAMUT, c->idx); if (!ret) c->ops.setup_vig_gamut = reg_dmav1_setup_vig_gamutv6; else c->ops.setup_vig_gamut = NULL; } } if (test_bit(SDE_SSPP_VIG_IGC, &features)) { Loading