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Commit ad4d35f8 authored by Yijing Wang's avatar Yijing Wang Committed by Bjorn Helgaas
Browse files

[SCSI] csiostor: Use pcie_capability_clear_and_set_word() to simplify code 



pci_is_pcie() and pcie_capability_clear_and_set_word() make it trivial
to set the PCIe Completion Timeout, so just fold the
csio_set_pcie_completion_timeout() function into its caller.

[bhelgaas: changelog, fold csio_set_pcie_completion_timeout() into caller]
Signed-off-by: default avatarYijing Wang <wangyijing@huawei.com>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Cc: Jiang Liu <jiang.liu@huawei.com>
Cc: "James E.J. Bottomley" <JBottomley@parallels.com>
Cc: Naresh Kumar Inna <naresh@chelsio.com>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Jesper Juhl <jj@chaosbits.net>
parent c0102c00

drivers/scsi/csiostor/csio_hw.c

+4 −18
Original line number Diff line number Diff line
@@ -852,22 +852,6 @@ csio_hw_get_flash_params(struct csio_hw *hw) 
	return 0;

}



static void

csio_set_pcie_completion_timeout(struct csio_hw *hw, u8 range)

{

	uint16_t val;

	int pcie_cap;



	if (!csio_pci_capability(hw->pdev, PCI_CAP_ID_EXP, &pcie_cap)) {

		pci_read_config_word(hw->pdev,

				     pcie_cap + PCI_EXP_DEVCTL2, &val);

		val &= 0xfff0;

		val |= range ;

		pci_write_config_word(hw->pdev,

				      pcie_cap + PCI_EXP_DEVCTL2, val);

	}

}



/*****************************************************************************/

/* HW State machine assists                                                  */

/*****************************************************************************/
@@ -2069,8 +2053,10 @@ csio_hw_configure(struct csio_hw *hw) 
		goto out;

	}



	/* Set pci completion timeout value to 4 seconds. */

	csio_set_pcie_completion_timeout(hw, 0xd);

	/* Set PCIe completion timeout to 4 seconds */

	if (pci_is_pcie(hw->pdev))

		pcie_capability_clear_and_set_word(hw->pdev, PCI_EXP_DEVCTL2,

				PCI_EXP_DEVCTL2_COMP_TIMEOUT, 0xd);



	hw->chip_ops->chip_set_mem_win(hw, MEMWIN_CSIOSTOR);

include/uapi/linux/pci_regs.h

+2 −1
Original line number Diff line number Diff line
@@ -558,7 +558,8 @@ 
#define  PCI_EXP_DEVCAP2_OBFF_MSG	0x00040000 /* New message signaling */

#define  PCI_EXP_DEVCAP2_OBFF_WAKE	0x00080000 /* Re-use WAKE# for OBFF */

#define PCI_EXP_DEVCTL2		40	/* Device Control 2 */

#define  PCI_EXP_DEVCTL2_ARI		0x20	/* Alternative Routing-ID */

#define  PCI_EXP_DEVCTL2_COMP_TIMEOUT	0x000f	/* Completion Timeout Value */

#define  PCI_EXP_DEVCTL2_ARI		0x0020	/* Alternative Routing-ID */

#define  PCI_EXP_DEVCTL2_IDO_REQ_EN	0x0100	/* Allow IDO for requests */

#define  PCI_EXP_DEVCTL2_IDO_CMP_EN	0x0200	/* Allow IDO for completions */

#define  PCI_EXP_DEVCTL2_LTR_EN		0x0400	/* Enable LTR mechanism */