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Commit acae7069 authored by Archana Sriram's avatar Archana Sriram
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msm: kgsl: Set correct values for SMMU protect register for A5xx 



For programming the CP Protect register for SMMU in A5xx, pass
correct values for SMMU registers base offset and the count of
registers to be protected.

Change-Id: Idbc377d1a03ee3b6cd3060c6feeeb95e04e859e9
Signed-off-by: default avatarArchana Sriram <apsrir@codeaurora.org>
parent c77acc02

drivers/gpu/msm/adreno_a5xx.c

+6 −3
Original line number Diff line number Diff line
@@ -353,12 +353,15 @@ static void a5xx_protect_init(struct adreno_device *adreno_dev) 
	/*

	 * For a530 and a540 the SMMU region is 0x20000 bytes long and 0x10000

	 * bytes on all other targets. The base offset for both is 0x40000.

	 * Write it to the next available slot

	 * Write it to the next available slot. The base offset and length of a

	 * block must be specified as power of 2 values.

	 */

	if (adreno_is_a530(adreno_dev) || adreno_is_a540(adreno_dev))

		_setprotectreg(device, reg + 1, 0x40000, ilog2(0x20000));

		_setprotectreg(device, reg + 1, (0x40000 >> 2),

			ilog2(0x20000 >> 2));

	else

		_setprotectreg(device, reg + 1, 0x40000, ilog2(0x10000));

		_setprotectreg(device, reg + 1, (0x40000 >> 2),

			ilog2(0x10000 >> 2));

}



/*