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Commit ac9aae00 authored by Anup Patel's avatar Anup Patel Committed by Florian Fainelli
Browse files

arm64: dts: Add SATA3 AHCI and SATA3 PHY DT nodes for NS2 



We have one dual-port SATA3 AHCI controller present in
NS2 SoC.

This patch enables SATA3 AHCI controller and SATA3 PHY
for NS2 SoC in NS2 DT.

Signed-off-by: default avatarAnup Patel <anup.patel@broadcom.com>
Reviewed-by: default avatarRay Jui <rjui@broadcom.com>
Reviewed-by: default avatarScott Branden <sbranden@broadcom.com>
Signed-off-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
parent 6e62688c

arch/arm64/boot/dts/broadcom/ns2-svk.dts

+12 −0
Original line number Diff line number Diff line
@@ -117,6 +117,18 @@ 
	};

};



&sata_phy0 {

	status = "ok";

};



&sata_phy1 {

	status = "ok";

};



&sata {

	status = "ok";

};



&sdio0 {

	status = "ok";

};

arch/arm64/boot/dts/broadcom/ns2.dtsi

+43 −0
Original line number Diff line number Diff line
@@ -368,6 +368,49 @@ 
			reg = <0x66220000 0x28>;

		};



		sata_phy: sata_phy@663f0100 {

			compatible = "brcm,iproc-ns2-sata-phy";

			reg = <0x663f0100 0x1f00>,

			      <0x663f004c 0x10>;

			reg-names = "phy", "phy-ctrl";

			#address-cells = <1>;

			#size-cells = <0>;



			sata_phy0: sata-phy@0 {

				reg = <0>;

				#phy-cells = <0>;

				status = "disabled";

			};



			sata_phy1: sata-phy@1 {

				reg = <1>;

				#phy-cells = <0>;

				status = "disabled";

			};

		};



		sata: ahci@663f2000 {

			compatible = "brcm,iproc-ahci", "generic-ahci";

			reg = <0x663f2000 0x1000>;

			reg-names = "ahci";

			interrupts = <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>;

			#address-cells = <1>;

			#size-cells = <0>;

			status = "disabled";



			sata0: sata-port@0 {

				reg = <0>;

				phys = <&sata_phy0>;

				phy-names = "sata-phy";

			};



			sata1: sata-port@1 {

				reg = <1>;

				phys = <&sata_phy1>;

				phy-names = "sata-phy";

			};

		};



		sdio0: sdhci@66420000 {

			compatible = "brcm,sdhci-iproc-cygnus";

			reg = <0x66420000 0x100>;