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Commit ac484963 authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Standardize on 'cpp' for bytes per pixel 



We more or less randomly call the "bytes per pixel" value
'cpp', 'bytes_per_pixel', 'pixel_size', or even 'bpp'. Let's just pick
one and stick to it. I've chosen 'cpp'.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1453316739-13296-6-git-send-email-ville.syrjala@linux.intel.com


Reviewed-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 54ea9da8

drivers/gpu/drm/i915/intel_display.c

+11 −11
Original line number Diff line number Diff line
@@ -2709,7 +2709,7 @@ static void i9xx_update_primary_plane(struct drm_plane *primary, 
	u32 linear_offset;

	u32 dspcntr;

	i915_reg_t reg = DSPCNTR(plane);

	int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);

	int cpp = drm_format_plane_cpp(fb->pixel_format, 0);

	int x = plane_state->src.x1 >> 16;

	int y = plane_state->src.y1 >> 16;
@@ -2769,13 +2769,12 @@ static void i9xx_update_primary_plane(struct drm_plane *primary, 
	if (IS_G4X(dev))

		dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;



	linear_offset = y * fb->pitches[0] + x * pixel_size;

	linear_offset = y * fb->pitches[0] + x * cpp;



	if (INTEL_INFO(dev)->gen >= 4) {

		intel_crtc->dspaddr_offset =

			intel_compute_tile_offset(dev_priv, &x, &y,

						  fb->modifier[0],

						  pixel_size,

						  fb->modifier[0], cpp,

						  fb->pitches[0]);

		linear_offset -= intel_crtc->dspaddr_offset;

	} else {
@@ -2792,7 +2791,7 @@ static void i9xx_update_primary_plane(struct drm_plane *primary, 
		data and adding to linear_offset*/

		linear_offset +=

			(crtc_state->pipe_src_h - 1) * fb->pitches[0] +

			(crtc_state->pipe_src_w - 1) * pixel_size;

			(crtc_state->pipe_src_w - 1) * cpp;

	}



	intel_crtc->adjusted_x = x;
@@ -2840,7 +2839,7 @@ static void ironlake_update_primary_plane(struct drm_plane *primary, 
	u32 linear_offset;

	u32 dspcntr;

	i915_reg_t reg = DSPCNTR(plane);

	int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);

	int cpp = drm_format_plane_cpp(fb->pixel_format, 0);

	int x = plane_state->src.x1 >> 16;

	int y = plane_state->src.y1 >> 16;
@@ -2879,11 +2878,10 @@ static void ironlake_update_primary_plane(struct drm_plane *primary, 
	if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))

		dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;



	linear_offset = y * fb->pitches[0] + x * pixel_size;

	linear_offset = y * fb->pitches[0] + x * cpp;

	intel_crtc->dspaddr_offset =

		intel_compute_tile_offset(dev_priv, &x, &y,

					  fb->modifier[0],

					  pixel_size,

					  fb->modifier[0], cpp,

					  fb->pitches[0]);

	linear_offset -= intel_crtc->dspaddr_offset;

	if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
@@ -2897,7 +2895,7 @@ static void ironlake_update_primary_plane(struct drm_plane *primary, 
			data and adding to linear_offset*/

			linear_offset +=

				(crtc_state->pipe_src_h - 1) * fb->pitches[0] +

				(crtc_state->pipe_src_w - 1) * pixel_size;

				(crtc_state->pipe_src_w - 1) * cpp;

		}

	}
@@ -14682,10 +14680,12 @@ u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier, 
	u32 gen = INTEL_INFO(dev)->gen;



	if (gen >= 9) {

		int cpp = drm_format_plane_cpp(pixel_format, 0);



		/* "The stride in bytes must not exceed the of the size of 8K

		 *  pixels and 32K bytes."

		 */

		 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);

		return min(8192 * cpp, 32768);

	} else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {

		return 32*1024;

	} else if (gen >= 4) {

drivers/gpu/drm/i915/intel_pm.c

+62 −66
Original line number Diff line number Diff line
@@ -548,7 +548,7 @@ static const struct intel_watermark_params i845_wm_info = { 
 * intel_calculate_wm - calculate watermark level

 * @clock_in_khz: pixel clock

 * @wm: chip FIFO params

 * @pixel_size: display pixel size

 * @cpp: bytes per pixel

 * @latency_ns: memory latency for the platform

 *

 * Calculate the watermark level (the level at which the display plane will
@@ -564,8 +564,7 @@ static const struct intel_watermark_params i845_wm_info = { 
 */

static unsigned long intel_calculate_wm(unsigned long clock_in_khz,

					const struct intel_watermark_params *wm,

					int fifo_size,

					int pixel_size,

					int fifo_size, int cpp,

					unsigned long latency_ns)

{

	long entries_required, wm_size;
@@ -576,7 +575,7 @@ static unsigned long intel_calculate_wm(unsigned long clock_in_khz, 
	 * clocks go from a few thousand to several hundred thousand.

	 * latency is usually a few thousand

	 */

	entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /

	entries_required = ((clock_in_khz / 1000) * cpp * latency_ns) /

		1000;

	entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
@@ -640,13 +639,13 @@ static void pineview_update_wm(struct drm_crtc *unused_crtc) 
	crtc = single_enabled_crtc(dev);

	if (crtc) {

		const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;

		int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;

		int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);

		int clock = adjusted_mode->crtc_clock;



		/* Display SR */

		wm = intel_calculate_wm(clock, &pineview_display_wm,

					pineview_display_wm.fifo_size,

					pixel_size, latency->display_sr);

					cpp, latency->display_sr);

		reg = I915_READ(DSPFW1);

		reg &= ~DSPFW_SR_MASK;

		reg |= FW_WM(wm, SR);
@@ -656,7 +655,7 @@ static void pineview_update_wm(struct drm_crtc *unused_crtc) 
		/* cursor SR */

		wm = intel_calculate_wm(clock, &pineview_cursor_wm,

					pineview_display_wm.fifo_size,

					pixel_size, latency->cursor_sr);

					cpp, latency->cursor_sr);

		reg = I915_READ(DSPFW3);

		reg &= ~DSPFW_CURSOR_SR_MASK;

		reg |= FW_WM(wm, CURSOR_SR);
@@ -665,7 +664,7 @@ static void pineview_update_wm(struct drm_crtc *unused_crtc) 
		/* Display HPLL off SR */

		wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,

					pineview_display_hplloff_wm.fifo_size,

					pixel_size, latency->display_hpll_disable);

					cpp, latency->display_hpll_disable);

		reg = I915_READ(DSPFW3);

		reg &= ~DSPFW_HPLL_SR_MASK;

		reg |= FW_WM(wm, HPLL_SR);
@@ -674,7 +673,7 @@ static void pineview_update_wm(struct drm_crtc *unused_crtc) 
		/* cursor HPLL off SR */

		wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,

					pineview_display_hplloff_wm.fifo_size,

					pixel_size, latency->cursor_hpll_disable);

					cpp, latency->cursor_hpll_disable);

		reg = I915_READ(DSPFW3);

		reg &= ~DSPFW_HPLL_CURSOR_MASK;

		reg |= FW_WM(wm, HPLL_CURSOR);
@@ -698,7 +697,7 @@ static bool g4x_compute_wm0(struct drm_device *dev, 
{

	struct drm_crtc *crtc;

	const struct drm_display_mode *adjusted_mode;

	int htotal, hdisplay, clock, pixel_size;

	int htotal, hdisplay, clock, cpp;

	int line_time_us, line_count;

	int entries, tlb_miss;
@@ -713,10 +712,10 @@ static bool g4x_compute_wm0(struct drm_device *dev, 
	clock = adjusted_mode->crtc_clock;

	htotal = adjusted_mode->crtc_htotal;

	hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;

	pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;

	cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);



	/* Use the small buffer method to calculate plane watermark */

	entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;

	entries = ((clock * cpp / 1000) * display_latency_ns) / 1000;

	tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;

	if (tlb_miss > 0)

		entries += tlb_miss;
@@ -728,7 +727,7 @@ static bool g4x_compute_wm0(struct drm_device *dev, 
	/* Use the large buffer method to calculate cursor watermark */

	line_time_us = max(htotal * 1000 / clock, 1);

	line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;

	entries = line_count * crtc->cursor->state->crtc_w * pixel_size;

	entries = line_count * crtc->cursor->state->crtc_w * cpp;

	tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;

	if (tlb_miss > 0)

		entries += tlb_miss;
@@ -784,7 +783,7 @@ static bool g4x_compute_srwm(struct drm_device *dev, 
{

	struct drm_crtc *crtc;

	const struct drm_display_mode *adjusted_mode;

	int hdisplay, htotal, pixel_size, clock;

	int hdisplay, htotal, cpp, clock;

	unsigned long line_time_us;

	int line_count, line_size;

	int small, large;
@@ -800,21 +799,21 @@ static bool g4x_compute_srwm(struct drm_device *dev, 
	clock = adjusted_mode->crtc_clock;

	htotal = adjusted_mode->crtc_htotal;

	hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;

	pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;

	cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);



	line_time_us = max(htotal * 1000 / clock, 1);

	line_count = (latency_ns / line_time_us + 1000) / 1000;

	line_size = hdisplay * pixel_size;

	line_size = hdisplay * cpp;



	/* Use the minimum of the small and large buffer method for primary */

	small = ((clock * pixel_size / 1000) * latency_ns) / 1000;

	small = ((clock * cpp / 1000) * latency_ns) / 1000;

	large = line_count * line_size;



	entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);

	*display_wm = entries + display->guard_size;



	/* calculate the self-refresh watermark for display cursor */

	entries = line_count * pixel_size * crtc->cursor->state->crtc_w;

	entries = line_count * cpp * crtc->cursor->state->crtc_w;

	entries = DIV_ROUND_UP(entries, cursor->cacheline_size);

	*cursor_wm = entries + cursor->guard_size;
@@ -906,13 +905,13 @@ enum vlv_wm_level { 
static unsigned int vlv_wm_method2(unsigned int pixel_rate,

				   unsigned int pipe_htotal,

				   unsigned int horiz_pixels,

				   unsigned int bytes_per_pixel,

				   unsigned int cpp,

				   unsigned int latency)

{

	unsigned int ret;



	ret = (latency * pixel_rate) / (pipe_htotal * 10000);

	ret = (ret + 1) * horiz_pixels * bytes_per_pixel;

	ret = (ret + 1) * horiz_pixels * cpp;

	ret = DIV_ROUND_UP(ret, 64);



	return ret;
@@ -941,7 +940,7 @@ static uint16_t vlv_compute_wm_level(struct intel_plane *plane, 
				     int level)

{

	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);

	int clock, htotal, pixel_size, width, wm;

	int clock, htotal, cpp, width, wm;



	if (dev_priv->wm.pri_latency[level] == 0)

		return USHRT_MAX;
@@ -949,7 +948,7 @@ static uint16_t vlv_compute_wm_level(struct intel_plane *plane, 
	if (!state->visible)

		return 0;



	pixel_size = drm_format_plane_cpp(state->base.fb->pixel_format, 0);

	cpp = drm_format_plane_cpp(state->base.fb->pixel_format, 0);

	clock = crtc->config->base.adjusted_mode.crtc_clock;

	htotal = crtc->config->base.adjusted_mode.crtc_htotal;

	width = crtc->config->pipe_src_w;
@@ -965,7 +964,7 @@ static uint16_t vlv_compute_wm_level(struct intel_plane *plane, 
		 */

		wm = 63;

	} else {

		wm = vlv_wm_method2(clock, htotal, width, pixel_size,

		wm = vlv_wm_method2(clock, htotal, width, cpp,

				    dev_priv->wm.pri_latency[level] * 10);

	}
@@ -1439,7 +1438,7 @@ static void i965_update_wm(struct drm_crtc *unused_crtc) 
		int clock = adjusted_mode->crtc_clock;

		int htotal = adjusted_mode->crtc_htotal;

		int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;

		int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;

		int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);

		unsigned long line_time_us;

		int entries;
@@ -1447,7 +1446,7 @@ static void i965_update_wm(struct drm_crtc *unused_crtc) 


		/* Use ns/us then divide to preserve precision */

		entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *

			pixel_size * hdisplay;

			cpp * hdisplay;

		entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);

		srwm = I965_FIFO_SIZE - entries;

		if (srwm < 0)
@@ -1457,7 +1456,7 @@ static void i965_update_wm(struct drm_crtc *unused_crtc) 
			      entries, srwm);



		entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *

			pixel_size * crtc->cursor->state->crtc_w;

			cpp * crtc->cursor->state->crtc_w;

		entries = DIV_ROUND_UP(entries,

					  i965_cursor_wm_info.cacheline_size);

		cursor_sr = i965_cursor_wm_info.fifo_size -
@@ -1518,7 +1517,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc) 
	crtc = intel_get_crtc_for_plane(dev, 0);

	if (intel_crtc_active(crtc)) {

		const struct drm_display_mode *adjusted_mode;

		int cpp = crtc->primary->state->fb->bits_per_pixel / 8;

		int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);

		if (IS_GEN2(dev))

			cpp = 4;
@@ -1540,7 +1539,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc) 
	crtc = intel_get_crtc_for_plane(dev, 1);

	if (intel_crtc_active(crtc)) {

		const struct drm_display_mode *adjusted_mode;

		int cpp = crtc->primary->state->fb->bits_per_pixel / 8;

		int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);

		if (IS_GEN2(dev))

			cpp = 4;
@@ -1586,7 +1585,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc) 
		int clock = adjusted_mode->crtc_clock;

		int htotal = adjusted_mode->crtc_htotal;

		int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;

		int pixel_size = enabled->primary->state->fb->bits_per_pixel / 8;

		int cpp = drm_format_plane_cpp(enabled->primary->state->fb->pixel_format, 0);

		unsigned long line_time_us;

		int entries;
@@ -1594,7 +1593,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc) 


		/* Use ns/us then divide to preserve precision */

		entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *

			pixel_size * hdisplay;

			cpp * hdisplay;

		entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);

		DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);

		srwm = wm_info->fifo_size - entries;
@@ -1685,15 +1684,14 @@ uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config) 
}



/* latency must be in 0.1us units. */

static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,

			       uint32_t latency)

static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)

{

	uint64_t ret;



	if (WARN(latency == 0, "Latency value missing\n"))

		return UINT_MAX;



	ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;

	ret = (uint64_t) pixel_rate * cpp * latency;

	ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;



	return ret;
@@ -1701,7 +1699,7 @@ static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel, 


/* latency must be in 0.1us units. */

static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,

			       uint32_t horiz_pixels, uint8_t bytes_per_pixel,

			       uint32_t horiz_pixels, uint8_t cpp,

			       uint32_t latency)

{

	uint32_t ret;
@@ -1712,13 +1710,13 @@ static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal, 
		return UINT_MAX;



	ret = (latency * pixel_rate) / (pipe_htotal * 10000);

	ret = (ret + 1) * horiz_pixels * bytes_per_pixel;

	ret = (ret + 1) * horiz_pixels * cpp;

	ret = DIV_ROUND_UP(ret, 64) + 2;

	return ret;

}



static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,

			   uint8_t bytes_per_pixel)

			   uint8_t cpp)

{

	/*

	 * Neither of these should be possible since this function shouldn't be
@@ -1726,12 +1724,12 @@ static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels, 
	 * extra paranoid to avoid a potential divide-by-zero if we screw up

	 * elsewhere in the driver.

	 */

	if (WARN_ON(!bytes_per_pixel))

	if (WARN_ON(!cpp))

		return 0;

	if (WARN_ON(!horiz_pixels))

		return 0;



	return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;

	return DIV_ROUND_UP(pri_val * 64, horiz_pixels * cpp) + 2;

}



struct ilk_wm_maximums {
@@ -1750,13 +1748,14 @@ static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate, 
				   uint32_t mem_value,

				   bool is_lp)

{

	int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;

	int cpp = pstate->base.fb ?

		drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;

	uint32_t method1, method2;



	if (!cstate->base.active || !pstate->visible)

		return 0;



	method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), bpp, mem_value);

	method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);



	if (!is_lp)

		return method1;
@@ -1764,8 +1763,7 @@ static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate, 
	method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),

				 cstate->base.adjusted_mode.crtc_htotal,

				 drm_rect_width(&pstate->dst),

				 bpp,

				 mem_value);

				 cpp, mem_value);



	return min(method1, method2);

}
@@ -1778,18 +1776,18 @@ static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate, 
				   const struct intel_plane_state *pstate,

				   uint32_t mem_value)

{

	int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;

	int cpp = pstate->base.fb ?

		drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;

	uint32_t method1, method2;



	if (!cstate->base.active || !pstate->visible)

		return 0;



	method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), bpp, mem_value);

	method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);

	method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),

				 cstate->base.adjusted_mode.crtc_htotal,

				 drm_rect_width(&pstate->dst),

				 bpp,

				 mem_value);

				 cpp, mem_value);

	return min(method1, method2);

}
@@ -1801,7 +1799,8 @@ static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate, 
				   const struct intel_plane_state *pstate,

				   uint32_t mem_value)

{

	int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;

	int cpp = pstate->base.fb ?

		drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;



	if (!cstate->base.active || !pstate->visible)

		return 0;
@@ -1809,8 +1808,7 @@ static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate, 
	return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),

			      cstate->base.adjusted_mode.crtc_htotal,

			      drm_rect_width(&pstate->dst),

			      bpp,

			      mem_value);

			      cpp, mem_value);

}



/* Only for WM_LP. */
@@ -1818,12 +1816,13 @@ static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate, 
				   const struct intel_plane_state *pstate,

				   uint32_t pri_val)

{

	int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;

	int cpp = pstate->base.fb ?

		drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;



	if (!cstate->base.active || !pstate->visible)

		return 0;



	return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->dst), bpp);

	return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->dst), cpp);

}



static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
@@ -3042,26 +3041,25 @@ static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config) 


/*

 * The max latency should be 257 (max the punit can code is 255 and we add 2us

 * for the read latency) and bytes_per_pixel should always be <= 8, so that

 * for the read latency) and cpp should always be <= 8, so that

 * should allow pixel_rate up to ~2 GHz which seems sufficient since max

 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.

*/

static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,

			       uint32_t latency)

static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)

{

	uint32_t wm_intermediate_val, ret;



	if (latency == 0)

		return UINT_MAX;



	wm_intermediate_val = latency * pixel_rate * bytes_per_pixel / 512;

	wm_intermediate_val = latency * pixel_rate * cpp / 512;

	ret = DIV_ROUND_UP(wm_intermediate_val, 1000);



	return ret;

}



static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,

			       uint32_t horiz_pixels, uint8_t bytes_per_pixel,

			       uint32_t horiz_pixels, uint8_t cpp,

			       uint64_t tiling, uint32_t latency)

{

	uint32_t ret;
@@ -3071,7 +3069,7 @@ static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal, 
	if (latency == 0)

		return UINT_MAX;



	plane_bytes_per_line = horiz_pixels * bytes_per_pixel;

	plane_bytes_per_line = horiz_pixels * cpp;



	if (tiling == I915_FORMAT_MOD_Y_TILED ||

	    tiling == I915_FORMAT_MOD_Yf_TILED) {
@@ -3121,23 +3119,21 @@ static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv, 
	uint32_t plane_bytes_per_line, plane_blocks_per_line;

	uint32_t res_blocks, res_lines;

	uint32_t selected_result;

	uint8_t bytes_per_pixel;

	uint8_t cpp;



	if (latency == 0 || !cstate->base.active || !fb)

		return false;



	bytes_per_pixel = drm_format_plane_cpp(fb->pixel_format, 0);

	cpp = drm_format_plane_cpp(fb->pixel_format, 0);

	method1 = skl_wm_method1(skl_pipe_pixel_rate(cstate),

				 bytes_per_pixel,

				 latency);

				 cpp, latency);

	method2 = skl_wm_method2(skl_pipe_pixel_rate(cstate),

				 cstate->base.adjusted_mode.crtc_htotal,

				 cstate->pipe_src_w,

				 bytes_per_pixel,

				 fb->modifier[0],

				 cpp, fb->modifier[0],

				 latency);



	plane_bytes_per_line = cstate->pipe_src_w * bytes_per_pixel;

	plane_bytes_per_line = cstate->pipe_src_w * cpp;

	plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);



	if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
@@ -3145,11 +3141,11 @@ static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv, 
		uint32_t min_scanlines = 4;

		uint32_t y_tile_minimum;

		if (intel_rotation_90_or_270(plane->state->rotation)) {

			int bpp = (fb->pixel_format == DRM_FORMAT_NV12) ?

			int cpp = (fb->pixel_format == DRM_FORMAT_NV12) ?

				drm_format_plane_cpp(fb->pixel_format, 1) :

				drm_format_plane_cpp(fb->pixel_format, 0);



			switch (bpp) {

			switch (cpp) {

			case 1:

				min_scanlines = 16;

				break;

drivers/gpu/drm/i915/intel_sprite.c

+14 −20
Original line number Diff line number Diff line
@@ -351,7 +351,7 @@ vlv_update_plane(struct drm_plane *dplane, 
	int plane = intel_plane->plane;

	u32 sprctl;

	u32 sprsurf_offset, linear_offset;

	int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);

	int cpp = drm_format_plane_cpp(fb->pixel_format, 0);

	const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;

	int crtc_x = plane_state->dst.x1;

	int crtc_y = plane_state->dst.y1;
@@ -422,10 +422,9 @@ vlv_update_plane(struct drm_plane *dplane, 
	crtc_w--;

	crtc_h--;



	linear_offset = y * fb->pitches[0] + x * pixel_size;

	linear_offset = y * fb->pitches[0] + x * cpp;

	sprsurf_offset = intel_compute_tile_offset(dev_priv, &x, &y,

						   fb->modifier[0],

						   pixel_size,

						   fb->modifier[0], cpp,

						   fb->pitches[0]);

	linear_offset -= sprsurf_offset;
@@ -434,7 +433,7 @@ vlv_update_plane(struct drm_plane *dplane, 


		x += src_w;

		y += src_h;

		linear_offset += src_h * fb->pitches[0] + src_w * pixel_size;

		linear_offset += src_h * fb->pitches[0] + src_w * cpp;

	}



	if (key->flags) {
@@ -494,7 +493,7 @@ ivb_update_plane(struct drm_plane *plane, 
	enum pipe pipe = intel_plane->pipe;

	u32 sprctl, sprscale = 0;

	u32 sprsurf_offset, linear_offset;

	int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);

	int cpp = drm_format_plane_cpp(fb->pixel_format, 0);

	const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;

	int crtc_x = plane_state->dst.x1;

	int crtc_y = plane_state->dst.y1;
@@ -556,10 +555,9 @@ ivb_update_plane(struct drm_plane *plane, 
	if (crtc_w != src_w || crtc_h != src_h)

		sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;



	linear_offset = y * fb->pitches[0] + x * pixel_size;

	linear_offset = y * fb->pitches[0] + x * cpp;

	sprsurf_offset = intel_compute_tile_offset(dev_priv, &x, &y,

						   fb->modifier[0],

						   pixel_size,

						   fb->modifier[0], cpp,

						   fb->pitches[0]);

	linear_offset -= sprsurf_offset;
@@ -570,8 +568,7 @@ ivb_update_plane(struct drm_plane *plane, 
		if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {

			x += src_w;

			y += src_h;

			linear_offset += src_h * fb->pitches[0] +

				src_w * pixel_size;

			linear_offset += src_h * fb->pitches[0] + src_w * cpp;

		}

	}
@@ -637,7 +634,7 @@ ilk_update_plane(struct drm_plane *plane, 
	int pipe = intel_plane->pipe;

	u32 dvscntr, dvsscale;

	u32 dvssurf_offset, linear_offset;

	int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);

	int cpp = drm_format_plane_cpp(fb->pixel_format, 0);

	const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;

	int crtc_x = plane_state->dst.x1;

	int crtc_y = plane_state->dst.y1;
@@ -695,10 +692,9 @@ ilk_update_plane(struct drm_plane *plane, 
	if (crtc_w != src_w || crtc_h != src_h)

		dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;



	linear_offset = y * fb->pitches[0] + x * pixel_size;

	linear_offset = y * fb->pitches[0] + x * cpp;

	dvssurf_offset = intel_compute_tile_offset(dev_priv, &x, &y,

						   fb->modifier[0],

						   pixel_size,

						   fb->modifier[0], cpp,

						   fb->pitches[0]);

	linear_offset -= dvssurf_offset;
@@ -707,7 +703,7 @@ ilk_update_plane(struct drm_plane *plane, 


		x += src_w;

		y += src_h;

		linear_offset += src_h * fb->pitches[0] + src_w * pixel_size;

		linear_offset += src_h * fb->pitches[0] + src_w * cpp;

	}



	if (key->flags) {
@@ -772,7 +768,6 @@ intel_check_sprite_plane(struct drm_plane *plane, 
	int hscale, vscale;

	int max_scale, min_scale;

	bool can_scale;

	int pixel_size;



	if (!fb) {

		state->visible = false;
@@ -894,6 +889,7 @@ intel_check_sprite_plane(struct drm_plane *plane, 
	/* Check size restrictions when scaling */

	if (state->visible && (src_w != crtc_w || src_h != crtc_h)) {

		unsigned int width_bytes;

		int cpp = drm_format_plane_cpp(fb->pixel_format, 0);



		WARN_ON(!can_scale);
@@ -905,9 +901,7 @@ intel_check_sprite_plane(struct drm_plane *plane, 
		if (src_w < 3 || src_h < 3)

			state->visible = false;



		pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);

		width_bytes = ((src_x * pixel_size) & 63) +

					src_w * pixel_size;

		width_bytes = ((src_x * cpp) & 63) + src_w * cpp;



		if (INTEL_INFO(dev)->gen < 9 && (src_w > 2048 || src_h > 2048 ||

		    width_bytes > 4096 || fb->pitches[0] > 4096)) {