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Commit abe11dde authored by Vineet Gupta's avatar Vineet Gupta
Browse files

ARC: [plat-arcfpga]: Enabling DeviceTree for Angel4 board 



* arc-uart platform device now populated dynamically, using
  of_platform_populate() - applies to any other device whatsoever.

* uart in turn requires incore arc-intc to be also present in DT

* A irq-domain needs to be instantiated for IRQ requests by DT probed
  device (e.g. arc-uart)

TODO: switch over to linear irq domain once all devs have been
      transitioned to DT

Signed-off-by: default avatarVineet Gupta <vgupta@synopsys.com>
Cc: Grant Likely <grant.likely@secretlab.ca>
Cc: Arnd Bergmann <arnd@arndb.de>
parent 450dd430

Documentation/devicetree/bindings/arc/interrupts.txt

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* ARC700 incore Interrupt Controller



  The core interrupt controller provides 32 prioritised interrupts (2 levels)

  to ARC700 core.



Properties:



- compatible: "snps,arc700-intc"

- interrupt-controller: This is an interrupt controller.

- #interrupt-cells: Must be <1>.



  Single Cell "interrupts" property of a device specifies the IRQ number

  between 0 to 31



  intc accessed via the special ARC AUX register interface, hence "reg" property

  is not specified.



Example:



	intc: interrupt-controller {

		compatible = "snps,arc700-intc";

		interrupt-controller;

		#interrupt-cells = <1>;

	};

arch/arc/boot/dts/Makefile

+1 −1
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# Built-in dtb

builtindtb-y		:= skeleton

builtindtb-y		:= angel4



ifneq ($(CONFIG_ARC_BUILTIN_DTB_NAME),"")

	builtindtb-y	:= $(patsubst "%",%,$(CONFIG_ARC_BUILTIN_DTB_NAME))

arch/arc/boot/dts/angel4.dts

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/*

 * Copyright (C) 2012 Synopsys, Inc. (www.synopsys.com)

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 */

/dts-v1/;



/include/ "skeleton.dtsi"



/ {

	compatible = "snps,arc-angel4";

	clock-frequency = <80000000>;	/* 80 MHZ */

	#address-cells = <1>;

	#size-cells = <1>;

	interrupt-parent = <&intc>;



	chosen {

		bootargs = "console=ttyARC0,115200n8";

	};



	aliases {

		serial0 = &arcuart0;

	};



	memory {

		device_type = "memory";

		reg = <0x00000000 0x10000000>;	/* 256M */

	};



	fpga {

		compatible = "simple-bus";

		#address-cells = <1>;

		#size-cells = <1>;



		/* child and parent address space 1:1 mapped */

		ranges;



		intc: interrupt-controller {

			compatible = "snps,arc700-intc";

			interrupt-controller;

			#interrupt-cells = <1>;

		};



		arcuart0: serial@c0fc1000 {

			compatible = "snps,arc-uart";

			reg = <0xc0fc1000 0x100>;

			interrupts = <5>;

			clock-frequency = <80000000>;

			baud = <115200>;

			status = "okay";

		};

	};

};

arch/arc/boot/dts/skeleton.dtsi

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@@ -18,6 +18,18 @@ 
	#size-cells = <1>;

	chosen { };

	aliases { };



	cpus {

		#address-cells = <1>;

		#size-cells = <0>;



		cpu@0 {

			device_type = "cpu";

			compatible = "snps,arc770d";

			reg = <0>;

		};

	};



	memory {

		device_type = "memory";

		reg = <0x00000000 0x10000000>;	/* 256M */

arch/arc/kernel/irq.c

+32 −6
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@@ -9,6 +9,8 @@ 


#include <linux/interrupt.h>

#include <linux/module.h>

#include <linux/of.h>

#include <linux/irqdomain.h>

#include <asm/sections.h>

#include <asm/irq.h>
@@ -59,16 +61,40 @@ static struct irq_chip onchip_intc = { 
	.irq_unmask	= arc_unmask_irq,

};



static int arc_intc_domain_map(struct irq_domain *d, unsigned int irq,

				irq_hw_number_t hw)

{

	if (irq == TIMER0_IRQ)

		irq_set_chip_and_handler(irq, &onchip_intc, handle_percpu_irq);

	else

		irq_set_chip_and_handler(irq, &onchip_intc, handle_level_irq);



	return 0;

}



static const struct irq_domain_ops arc_intc_domain_ops = {

	.xlate = irq_domain_xlate_onecell,

	.map = arc_intc_domain_map,

};



static struct irq_domain *root_domain;



void __init init_onchip_IRQ(void)

{

	int i;

	struct device_node *intc = NULL;



	intc = of_find_compatible_node(NULL, NULL, "snps,arc700-intc");

	if(!intc)

		panic("DeviceTree Missing incore intc\n");



	root_domain = irq_domain_add_legacy(intc, NR_IRQS, 0, 0,

					    &arc_intc_domain_ops, NULL);



	for (i = 0; i < NR_IRQS; i++)

		irq_set_chip_and_handler(i, &onchip_intc, handle_level_irq);

	if (!root_domain)

		panic("root irq domain not avail\n");



#ifdef CONFIG_SMP

	irq_set_chip_and_handler(TIMER0_IRQ, &onchip_intc, handle_percpu_irq);

#endif

	/* with this we don't need to export root_domain */

	irq_set_default_host(root_domain);

}



/*