Commit ab9e00ce authored May 29, 2020 by Taniya Das

clk: qcom: gcc: Lower OPE clock frequency to 576MHz



There is a RCG frequency overshoot during the switch from gpll8 early
output to main output, which is causing OPE clock to hang. Thus derive
the turbo frequency from GPLL9.

Change-Id: Ia125b5dde04630950697adac4cdbfc7a331cfc28
Signed-off-by: Taniya Das <tdas@codeaurora.org>

parent 1d6a7b7e

drivers/clk/qcom/gcc-bengal.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -1082,7 +1082,7 @@ static const struct freq_tbl ftbl_gcc_camss_ope_clk_src[] = {
		F(200000000, P_GPLL8_OUT_MAIN, 2, 0, 0),
		F(266600000, P_GPLL8_OUT_MAIN, 1, 0, 0),
		F(465000000, P_GPLL8_OUT_MAIN, 1, 0, 0),
		F(580000000, P_GPLL8_OUT_EARLY, 1, 0, 0),
		F(576000000, P_GPLL9_OUT_MAIN, 1, 0, 0),
		{ }
		};