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Commit ab3759b5 authored by Simon Guo's avatar Simon Guo Committed by Michael Ellerman
Browse files

powerpc/reg: Add TEXASR related macros 



This patches add some macros for CR0/TEXASR bits so that PR KVM TM
logic (tbegin./treclaim./tabort.) can make use of them later.

Signed-off-by: default avatarSimon Guo <wei.guo.simon@gmail.com>
Reviewed-by: default avatarPaul Mackerras <paulus@ozlabs.org>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
parent d1c72112

arch/powerpc/include/asm/reg.h

+26 −6
Original line number Diff line number Diff line
@@ -146,6 +146,12 @@ 
#define MSR_64BIT	0

#endif



/* Condition Register related */

#define CR0_SHIFT	28

#define CR0_MASK	0xF

#define CR0_TBEGIN_FAILURE	(0x2 << 28) /* 0b0010 */





/* Power Management - Processor Stop Status and Control Register Fields */

#define PSSCR_RL_MASK		0x0000000F /* Requested Level */

#define PSSCR_MTL_MASK		0x000000F0 /* Maximum Transition Level */
@@ -239,13 +245,27 @@ 
#define SPRN_TFIAR	0x81	/* Transaction Failure Inst Addr   */

#define SPRN_TEXASR	0x82	/* Transaction EXception & Summary */

#define SPRN_TEXASRU	0x83	/* ''	   ''	   ''	 Upper 32  */

#define   TEXASR_ABORT	__MASK(63-31) /* terminated by tabort or treclaim */

#define   TEXASR_SUSP	__MASK(63-32) /* tx failed in suspended state */

#define   TEXASR_HV	__MASK(63-34) /* MSR[HV] when failure occurred */

#define   TEXASR_PR	__MASK(63-35) /* MSR[PR] when failure occurred */

#define   TEXASR_FS	__MASK(63-36) /* TEXASR Failure Summary */

#define   TEXASR_EXACT	__MASK(63-37) /* TFIAR value is exact */



#define TEXASR_FC_LG	(63 - 7)	/* Failure Code */

#define TEXASR_AB_LG	(63 - 31)	/* Abort */

#define TEXASR_SU_LG	(63 - 32)	/* Suspend */

#define TEXASR_HV_LG	(63 - 34)	/* Hypervisor state*/

#define TEXASR_PR_LG	(63 - 35)	/* Privilege level */

#define TEXASR_FS_LG	(63 - 36)	/* failure summary */

#define TEXASR_EX_LG	(63 - 37)	/* TFIAR exact bit */

#define TEXASR_ROT_LG	(63 - 38)	/* ROT bit */



#define   TEXASR_ABORT	__MASK(TEXASR_AB_LG) /* terminated by tabort or treclaim */

#define   TEXASR_SUSP	__MASK(TEXASR_SU_LG) /* tx failed in suspended state */

#define   TEXASR_HV	__MASK(TEXASR_HV_LG) /* MSR[HV] when failure occurred */

#define   TEXASR_PR	__MASK(TEXASR_PR_LG) /* MSR[PR] when failure occurred */

#define   TEXASR_FS	__MASK(TEXASR_FS_LG) /* TEXASR Failure Summary */

#define   TEXASR_EXACT	__MASK(TEXASR_EX_LG) /* TFIAR value is exact */

#define   TEXASR_ROT	__MASK(TEXASR_ROT_LG)

#define   TEXASR_FC	(ASM_CONST(0xFF) << TEXASR_FC_LG)



#define SPRN_TFHAR	0x80	/* Transaction Failure Handler Addr */



#define SPRN_TIDR	144	/* Thread ID register */

#define SPRN_CTRLF	0x088

#define SPRN_CTRLT	0x098

arch/powerpc/platforms/powernv/copy-paste.h

+1 −2
Original line number Diff line number Diff line
@@ -7,9 +7,8 @@ 
 * 2 of the License, or (at your option) any later version.

 */

#include <asm/ppc-opcode.h>

#include <asm/reg.h>



#define CR0_SHIFT	28

#define CR0_MASK	0xF

/*

 * Copy/paste instructions:

 *