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Commit ab1ad2bb authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "msm: mdss: update the DSI 12nm PHY programming sequence"

parents 3c4d7170 68e83305

drivers/video/fbdev/msm/mdss_dsi_phy_12nm.c

+4 −1
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/* Copyright (c) 2018, 2020, The Linux Foundation. All rights reserved. */

/* Copyright (c) 2018, 2020-2021, The Linux Foundation. All rights reserved. */



#include <linux/iopoll.h>

#include "mdss_dsi_phy.h"
@@ -15,6 +15,7 @@ 
#define HSTX_CLKLANE_REQSTATE_TIM_CTRL       0x180

#define HSTX_CLKLANE_HS0STATE_TIM_CTRL       0x188

#define HSTX_CLKLANE_TRALSTATE_TIM_CTRL      0x18c

#define HSTX_CLKLANE_EXITSTATE_TIM_CTRL      0x190

#define HSTX_CLKLANE_CLKPOSTSTATE_TIM_CTRL   0x194

#define HSTX_DATALANE_REQSTATE_TIM_CTRL      0x1c0

#define HSTX_DATALANE_HS0STATE_TIM_CTRL      0x1c8
@@ -60,6 +61,8 @@ int mdss_dsi_12nm_phy_config(struct mdss_dsi_ctrl_pdata *ctrl) 
		(pd->timing_12nm[2] | BIT(6)));

	DSI_PHY_W32(ctrl->phy_io.base, HSTX_CLKLANE_REQSTATE_TIM_CTRL,

		pd->timing_12nm[3]);

	DSI_PHY_W32(ctrl->phy_io.base, HSTX_CLKLANE_EXITSTATE_TIM_CTRL,

		(pd->timing_12nm[7] | BIT(6) | BIT(7)));



	/* DSI PHY data lane timings */

	DSI_PHY_W32(ctrl->phy_io.base, HSTX_DATALANE_HS0STATE_TIM_CTRL,