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Commit aa8ac92a authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "msm: kgsl: Correctly handle dcvs hfi failures"

parents 6c26af96 83b78fc6

drivers/gpu/msm/adreno.h

+1 −0
Original line number Diff line number Diff line
@@ -214,6 +214,7 @@ enum adreno_gpurev { 
#define ADRENO_PREEMPT_FAULT BIT(4)

#define ADRENO_GMU_FAULT BIT(5)

#define ADRENO_CTX_DETATCH_TIMEOUT_FAULT BIT(6)

#define ADRENO_GMU_FAULT_SKIP_SNAPSHOT BIT(7)



#define ADRENO_SPTP_PC_CTRL 0

#define ADRENO_LM_CTRL      1

drivers/gpu/msm/adreno_dispatch.c

+2 −1
Original line number Diff line number Diff line
@@ -2198,6 +2198,7 @@ static int dispatcher_do_fault(struct adreno_device *adreno_dev) 
		&adreno_dev->ft_pf_policy) && adreno_dev->cooperative_reset)

		gmu_core_dev_cooperative_reset(device);



	if (!(fault & ADRENO_GMU_FAULT_SKIP_SNAPSHOT))

		do_header_and_snapshot(device, fault, hung_rb, cmdobj);



	/* Turn off the KEEPALIVE vote from the ISR for hard fault */

drivers/gpu/msm/kgsl_gmu.c

+23 −3
Original line number Diff line number Diff line
@@ -537,7 +537,22 @@ static int gmu_dcvs_set(struct kgsl_device *device, 
		dev_err_ratelimited(&gmu->pdev->dev,

			"Failed to set GPU perf idx %d, bw idx %d\n",

			req.freq, req.bw);

		gmu_snapshot(device);



		/*

		 * We can be here in two situations. First, we send a dcvs

		 * hfi so gmu knows at what level it must bring up the gpu.

		 * If that fails, it is already being handled as part of

		 * gmu boot failures. The other reason why we are here is

		 * because we are trying to scale an active gpu. For this,

		 * we need to do inline snapshot and dispatcher based

		 * recovery.

		 */

		if (test_bit(ADRENO_DEVICE_STARTED, &adreno_dev->priv)) {

			gmu_core_snapshot(device);

			adreno_set_gpu_fault(adreno_dev, ADRENO_GMU_FAULT |

				ADRENO_GMU_FAULT_SKIP_SNAPSHOT);

			adreno_dispatcher_schedule(device);

		}

	}



	/* indicate actual clock change */
@@ -1593,7 +1608,10 @@ static int gmu_start(struct kgsl_device *device) 
			goto error_gmu;



		/* Request default DCVS level */

		kgsl_pwrctrl_set_default_gpu_pwrlevel(device);

		ret = kgsl_pwrctrl_set_default_gpu_pwrlevel(device);

		if (ret)

			goto error_gmu;



		msm_bus_scale_client_update_request(gmu->pcl, 0);

		break;
@@ -1613,7 +1631,9 @@ static int gmu_start(struct kgsl_device *device) 
		if (ret)

			goto error_gmu;



		kgsl_pwrctrl_set_default_gpu_pwrlevel(device);

		ret = kgsl_pwrctrl_set_default_gpu_pwrlevel(device);

		if (ret)

			goto error_gmu;

		break;



	case KGSL_STATE_RESET:

drivers/gpu/msm/kgsl_pwrctrl.c

+2 −2
Original line number Diff line number Diff line
@@ -3136,7 +3136,7 @@ EXPORT_SYMBOL(kgsl_pwr_limits_get_freq); 
 * kgsl_pwrctrl_set_default_gpu_pwrlevel() - Set GPU to default power level

 * @device: Pointer to the kgsl_device struct

 */

void kgsl_pwrctrl_set_default_gpu_pwrlevel(struct kgsl_device *device)

int kgsl_pwrctrl_set_default_gpu_pwrlevel(struct kgsl_device *device)

{

	struct kgsl_pwrctrl *pwr = &device->pwrctrl;

	unsigned int new_level = pwr->default_pwrlevel;
@@ -3158,5 +3158,5 @@ void kgsl_pwrctrl_set_default_gpu_pwrlevel(struct kgsl_device *device) 
	pwr->previous_pwrlevel = old_level;



	/* Request adjusted DCVS level */

	kgsl_clk_set_rate(device, pwr->active_pwrlevel);

	return kgsl_clk_set_rate(device, pwr->active_pwrlevel);

}

drivers/gpu/msm/kgsl_pwrctrl.h

+1 −1
Original line number Diff line number Diff line
@@ -267,7 +267,7 @@ void kgsl_pwrctrl_set_constraint(struct kgsl_device *device, 
			struct kgsl_pwr_constraint *pwrc, uint32_t id);

void kgsl_pwrctrl_update_l2pc(struct kgsl_device *device,

			unsigned long timeout_us);

void kgsl_pwrctrl_set_default_gpu_pwrlevel(struct kgsl_device *device);

int kgsl_pwrctrl_set_default_gpu_pwrlevel(struct kgsl_device *device);

void kgsl_pwrctrl_disable_unused_opp(struct kgsl_device *device,

		struct device *dev);