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Commit aa7ba5f3 authored by Elson Roy Serrao's avatar Elson Roy Serrao
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usb: dwc3: Enable PHY deep low power mode in L1 suspend 



Currently controller is enabling only shallow low power mode during
L1 suspend in host mode. Power savings can be improved by allowing
deep low power mode allowing PLL to be turned OFF. Configuring
the GUCTL1 register to enable this feature.

Change-Id: Iea6cfa2c9085a01f45a9f0d633c80368ad085806
Signed-off-by: default avatarElson Roy Serrao <eserrao@codeaurora.org>
parent 6b3ddc57

drivers/usb/dwc3/core.c

+8 −0
Original line number Original line Diff line number Diff line
@@ -145,6 +145,10 @@ void dwc3_en_sleep_mode(struct dwc3 *dwc) 
	reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));

	reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));

	reg |= DWC3_GUSB2PHYCFG_ENBLSLPM;

	reg |= DWC3_GUSB2PHYCFG_ENBLSLPM;

	dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);

	dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);



	reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);

	reg |= DWC3_GUCTL1_L1_SUSP_THRLD_EN_FOR_HOST;

	dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);

}

}





void dwc3_dis_sleep_mode(struct dwc3 *dwc)

void dwc3_dis_sleep_mode(struct dwc3 *dwc)
@@ -154,6 +158,10 @@ void dwc3_dis_sleep_mode(struct dwc3 *dwc) 
	reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));

	reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));

	reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;

	reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;

	dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);

	dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);



	reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);

	reg &= ~DWC3_GUCTL1_L1_SUSP_THRLD_EN_FOR_HOST;

	dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);

}

}





void dwc3_set_mode(struct dwc3 *dwc, u32 mode)

void dwc3_set_mode(struct dwc3 *dwc, u32 mode)

drivers/usb/dwc3/core.h

+1 −0
Original line number Original line Diff line number Diff line
@@ -258,6 +258,7 @@ 
#define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS	BIT(28)

#define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS	BIT(28)

#define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW	BIT(24)

#define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW	BIT(24)

#define DWC3_GUCTL1_IP_GAP_ADD_ON(n)	(n << 21)

#define DWC3_GUCTL1_IP_GAP_ADD_ON(n)	(n << 21)

#define DWC3_GUCTL1_L1_SUSP_THRLD_EN_FOR_HOST	BIT(8)





/* Global Status Register */

/* Global Status Register */

#define DWC3_GSTS_OTG_IP	BIT(10)

#define DWC3_GSTS_OTG_IP	BIT(10)