Merge "clk: qcom: Add additional clock debugfs support" (aa446fb2) · Commits · e / devices / android_kernel_fairphone_FP4

drivers/clk/qcom/clk-alpha-pll.c

+37 −0

Original line number	Diff line number	Diff line
		@@ -729,6 +729,41 @@ static long alpha_pll_huayra_round_rate(struct clk_hw *hw, unsigned long rate,
		return alpha_huayra_pll_round_rate(rate, *prate, &l, &a);
		}

		static void clk_alpha_pll_list_registers(struct seq_file f, struct clk_hw hw)
		{
		struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
		int size, i, val;

		static struct clk_register_data data[] = {
		{"PLL_MODE", 0x0},
		{"PLL_L_VAL", 0x4},
		{"PLL_ALPHA_VAL", 0x8},
		{"PLL_ALPHA_VAL_U", 0xC},
		{"PLL_USER_CTL", 0x10},
		{"PLL_CONFIG_CTL", 0x18},
		};

		static struct clk_register_data data1[] = {
		{"APSS_PLL_VOTE", 0x0},
		};

		size = ARRAY_SIZE(data);

		for (i = 0; i < size; i++) {
		regmap_read(pll->clkr.regmap, pll->offset + data[i].offset,
		&val);
		seq_printf(f, "%20s: 0x%.8x\n", data[i].name, val);
		}

		regmap_read(pll->clkr.regmap, pll->offset + data[0].offset, &val);

		if (val & PLL_FSM_ENA) {
		regmap_read(pll->clkr.regmap, pll->clkr.enable_reg +
		data1[0].offset, &val);
		seq_printf(f, "%20s: 0x%.8x\n", data1[0].name, val);
		}
		}

		const struct clk_ops clk_alpha_pll_ops = {
		.enable = clk_alpha_pll_enable,
		.disable = clk_alpha_pll_disable,
		@@ -736,6 +771,7 @@ const struct clk_ops clk_alpha_pll_ops = {
		.recalc_rate = clk_alpha_pll_recalc_rate,
		.round_rate = clk_alpha_pll_round_rate,
		.set_rate = clk_alpha_pll_set_rate,
		.list_registers = clk_alpha_pll_list_registers,
		};
		EXPORT_SYMBOL_GPL(clk_alpha_pll_ops);

		@@ -756,6 +792,7 @@ const struct clk_ops clk_alpha_pll_hwfsm_ops = {
		.recalc_rate = clk_alpha_pll_recalc_rate,
		.round_rate = clk_alpha_pll_round_rate,
		.set_rate = clk_alpha_pll_hwfsm_set_rate,
		.list_registers = clk_alpha_pll_list_registers,
		};
		EXPORT_SYMBOL_GPL(clk_alpha_pll_hwfsm_ops);

drivers/clk/qcom/clk-branch.c

+40 −1

Original line number	Diff line number	Diff line
		// SPDX-License-Identifier: GPL-2.0
		/*
		* Copyright (c) 2013, 2017, The Linux Foundation. All rights reserved.
		* Copyright (c) 2013, 2017-2018, The Linux Foundation. All rights reserved.
		*/

		#include <linux/kernel.h>
		@@ -14,6 +14,7 @@
		#include <linux/clk/qcom.h>

		#include "clk-branch.h"
		#include "clk-regmap.h"

		static bool clk_branch_in_hwcg_mode(const struct clk_branch *br)
		{
		@@ -299,6 +300,43 @@ static void clk_branch2_unprepare(struct clk_hw *hw)
		}
		}

		static void clk_branch2_list_registers(struct seq_file f, struct clk_hw hw)
		{
		struct clk_branch *br = to_clk_branch(hw);
		struct clk_regmap *rclk = to_clk_regmap(hw);
		int size, i, val;

		static struct clk_register_data data[] = {
		{"CBCR", 0x0},
		};

		static struct clk_register_data data1[] = {
		{"APSS_VOTE", 0x0},
		{"APSS_SLEEP_VOTE", 0x4},
		};

		size = ARRAY_SIZE(data);

		for (i = 0; i < size; i++) {
		regmap_read(br->clkr.regmap, br->halt_reg + data[i].offset,
		&val);
		seq_printf(f, "%20s: 0x%.8x\n", data[i].name, val);
		}

		if ((br->halt_check & BRANCH_HALT_VOTED) &&
		!(br->halt_check & BRANCH_VOTED)) {
		if (rclk->enable_reg) {
		size = ARRAY_SIZE(data1);
		for (i = 0; i < size; i++) {
		regmap_read(br->clkr.regmap, rclk->enable_reg +
		data1[i].offset, &val);
		seq_printf(f, "%20s: 0x%.8x\n",
		data1[i].name, val);
		}
		}
		}
		}

		const struct clk_ops clk_branch2_ops = {
		.prepare = clk_branch2_prepare,
		.enable = clk_branch2_enable,
		@@ -309,6 +347,7 @@ const struct clk_ops clk_branch2_ops = {
		.round_rate = clk_branch2_round_rate,
		.recalc_rate = clk_branch2_recalc_rate,
		.set_flags = clk_branch_set_flags,
		.list_registers = clk_branch2_list_registers,
		};
		EXPORT_SYMBOL_GPL(clk_branch2_ops);

drivers/clk/qcom/clk-rcg2.c

+66 −0

Original line number	Diff line number	Diff line
		@@ -395,6 +395,61 @@ static int clk_rcg2_configure(struct clk_rcg2 rcg, const struct freq_tbl f)
		return update_config(rcg);
		}

		static void clk_rcg2_list_registers(struct seq_file f, struct clk_hw hw)
		{
		struct clk_rcg2 *rcg = to_clk_rcg2(hw);
		int i = 0, size = 0, val;

		static struct clk_register_data data[] = {
		{"CMD_RCGR", 0x0},
		{"CFG_RCGR", 0x4},
		};

		static struct clk_register_data data1[] = {
		{"CMD_RCGR", 0x0},
		{"CFG_RCGR", 0x4},
		{"M_VAL", 0x8},
		{"N_VAL", 0xC},
		{"D_VAL", 0x10},
		};

		if (rcg->mnd_width) {
		size = ARRAY_SIZE(data1);
		for (i = 0; i < size; i++) {
		regmap_read(rcg->clkr.regmap, (rcg->cmd_rcgr +
		data1[i].offset), &val);
		seq_printf(f, "%20s: 0x%.8x\n", data1[i].name, val);
		}
		} else {
		size = ARRAY_SIZE(data);
		for (i = 0; i < size; i++) {
		regmap_read(rcg->clkr.regmap, (rcg->cmd_rcgr +
		data[i].offset), &val);
		seq_printf(f, "%20s: 0x%.8x\n", data[i].name, val);
		}
		}
		}

		/* Return the nth supported frequency for a given clock. */
		static long clk_rcg2_list_rate(struct clk_hw *hw, unsigned int n,
		unsigned long fmax)
		{
		struct clk_rcg2 *rcg = to_clk_rcg2(hw);
		const struct freq_tbl *f = rcg->freq_tbl;
		size_t freq_tbl_size = 0;

		if (!f)
		return -ENXIO;

		for (; f->freq; f++)
		freq_tbl_size++;

		if (n > freq_tbl_size - 1)
		return -EINVAL;

		return (rcg->freq_tbl + n)->freq;
		}

		static int __clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate,
		enum freq_policy policy)
		{
		@@ -578,6 +633,8 @@ const struct clk_ops clk_rcg2_ops = {
		.determine_rate = clk_rcg2_determine_rate,
		.set_rate = clk_rcg2_set_rate,
		.set_rate_and_parent = clk_rcg2_set_rate_and_parent,
		.list_rate = clk_rcg2_list_rate,
		.list_registers = clk_rcg2_list_registers,
		};
		EXPORT_SYMBOL_GPL(clk_rcg2_ops);

		@@ -589,6 +646,8 @@ const struct clk_ops clk_rcg2_floor_ops = {
		.determine_rate = clk_rcg2_determine_floor_rate,
		.set_rate = clk_rcg2_set_floor_rate,
		.set_rate_and_parent = clk_rcg2_set_floor_rate_and_parent,
		.list_rate = clk_rcg2_list_rate,
		.list_registers = clk_rcg2_list_registers,
		};
		EXPORT_SYMBOL_GPL(clk_rcg2_floor_ops);

		@@ -716,6 +775,7 @@ const struct clk_ops clk_edp_pixel_ops = {
		.set_rate = clk_edp_pixel_set_rate,
		.set_rate_and_parent = clk_edp_pixel_set_rate_and_parent,
		.determine_rate = clk_edp_pixel_determine_rate,
		.list_registers = clk_rcg2_list_registers,
		};
		EXPORT_SYMBOL_GPL(clk_edp_pixel_ops);

		@@ -774,6 +834,7 @@ const struct clk_ops clk_byte_ops = {
		.set_rate = clk_byte_set_rate,
		.set_rate_and_parent = clk_byte_set_rate_and_parent,
		.determine_rate = clk_byte_determine_rate,
		.list_registers = clk_rcg2_list_registers,
		};
		EXPORT_SYMBOL_GPL(clk_byte_ops);

		@@ -844,6 +905,7 @@ const struct clk_ops clk_byte2_ops = {
		.set_rate = clk_byte2_set_rate,
		.set_rate_and_parent = clk_byte2_set_rate_and_parent,
		.determine_rate = clk_byte2_determine_rate,
		.list_registers = clk_rcg2_list_registers,
		};
		EXPORT_SYMBOL_GPL(clk_byte2_ops);

		@@ -934,6 +996,7 @@ const struct clk_ops clk_pixel_ops = {
		.set_rate = clk_pixel_set_rate,
		.set_rate_and_parent = clk_pixel_set_rate_and_parent,
		.determine_rate = clk_pixel_determine_rate,
		.list_registers = clk_rcg2_list_registers,
		};
		EXPORT_SYMBOL_GPL(clk_pixel_ops);

		@@ -1017,6 +1080,7 @@ const struct clk_ops clk_dp_ops = {
		.set_rate = clk_dp_set_rate,
		.set_rate_and_parent = clk_dp_set_rate_and_parent,
		.determine_rate = clk_dp_determine_rate,
		.list_registers = clk_rcg2_list_registers,
		};
		EXPORT_SYMBOL_GPL(clk_dp_ops);

		@@ -1104,6 +1168,7 @@ const struct clk_ops clk_gfx3d_ops = {
		.set_rate = clk_gfx3d_set_rate,
		.set_rate_and_parent = clk_gfx3d_set_rate_and_parent,
		.determine_rate = clk_gfx3d_determine_rate,
		.list_registers = clk_rcg2_list_registers,
		};
		EXPORT_SYMBOL_GPL(clk_gfx3d_ops);

		@@ -1211,5 +1276,6 @@ const struct clk_ops clk_rcg2_shared_ops = {
		.determine_rate = clk_rcg2_determine_rate,
		.set_rate = clk_rcg2_shared_set_rate,
		.set_rate_and_parent = clk_rcg2_shared_set_rate_and_parent,
		.list_registers = clk_rcg2_list_registers,
		};
		EXPORT_SYMBOL_GPL(clk_rcg2_shared_ops);

drivers/clk/qcom/clk-regmap.h

+7 −1

Original line number	Diff line number	Diff line
		/* SPDX-License-Identifier: GPL-2.0 */
		/* Copyright (c) 2014, The Linux Foundation. All rights reserved. */
		/* Copyright (c) 2014, 2017, The Linux Foundation. All rights reserved. */

		#ifndef __QCOM_CLK_REGMAP_H__
		#define __QCOM_CLK_REGMAP_H__

		#include <linux/clk-provider.h>
		#include <linux/debugfs.h>

		struct regmap;

		@@ -31,4 +32,9 @@ int clk_enable_regmap(struct clk_hw *hw);
		void clk_disable_regmap(struct clk_hw *hw);
		int devm_clk_register_regmap(struct device dev, struct clk_regmap rclk);

		struct clk_register_data {
		char *name;
		u32 offset;
		};

		#endif