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Commit aa08ed55 authored by Aaro Koskinen's avatar Aaro Koskinen Committed by Ralf Baechle
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MIPS: loongson2_cpufreq: Fix CPU clock rate setting mismerge



During 3.16 merge window, parts of the commit 8e8acb32
(MIPS/loongson2_cpufreq: Fix CPU clock rate setting) seem to have
been deleted probably due to a mismerge, and as a result cpufreq
is broken again on Loongson2 boards in 3.16 and newer kernels.
Fix by repeating the fix.

Signed-off-by: default avatarAaro Koskinen <aaro.koskinen@iki.fi>
Cc: stable@vger.kernel.org # 3.16
Cc: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/7835/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 5a1e73ff
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+3 −2
Original line number Diff line number Diff line
@@ -91,6 +91,7 @@ EXPORT_SYMBOL(clk_put);

int clk_set_rate(struct clk *clk, unsigned long rate)
{
	unsigned int rate_khz = rate / 1000;
	struct cpufreq_frequency_table *pos;
	int ret = 0;
	int regval;
@@ -107,9 +108,9 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
		propagate_rate(clk);

	cpufreq_for_each_valid_entry(pos, loongson2_clockmod_table)
		if (rate == pos->frequency)
		if (rate_khz == pos->frequency)
			break;
	if (rate != pos->frequency)
	if (rate_khz != pos->frequency)
		return -ENOTSUPP;

	clk->rate = rate;