Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit a9cc726c authored by Daniel Vetter's avatar Daniel Vetter
Browse files

drm/i915: Handle set_cache_level errors in the pipe control scratch setup



Split out from Chris vma-bind rework.

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ben Widawsky <benjamin.widawsky@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent bf3d149b
Loading
Loading
Loading
Loading
+3 −1
Original line number Diff line number Diff line
@@ -531,7 +531,9 @@ init_pipe_control(struct intel_ring_buffer *ring)
		goto err;
	}

	i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC);
	ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC);
	if (ret)
		goto err_unref;

	ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0);
	if (ret)