Commit a96ac5cb authored Jun 17, 2019 by ShihPo Hung Committed by Greg Kroah-Hartman Jun 25, 2019

riscv: mm: synchronize MMU after pte change



commit bf587caae305ae3b4393077fb22c98478ee55755 upstream.

Because RISC-V compliant implementations can cache invalid entries
in TLB, an SFENCE.VMA is necessary after changes to the page table.
This patch adds an SFENCE.vma for the vmalloc_fault path.

Signed-off-by: ShihPo Hung <shihpo.hung@sifive.com>
[paul.walmsley@sifive.com: reversed tab->whitespace conversion,
 wrapped comment lines]
Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Albert Ou <aou@eecs.berkeley.edu>
Cc: Paul Walmsley <paul.walmsley@sifive.com>
Cc: linux-riscv@lists.infradead.org
Cc: stable@vger.kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

parent 5ad9a23e

arch/riscv/mm/fault.c

+13 −0

Original line number	Diff line number	Diff line
		@@ -29,6 +29,7 @@

		#include <asm/pgalloc.h>
		#include <asm/ptrace.h>
		#include <asm/tlbflush.h>

		/*
		* This routine handles page faults. It determines the address and the
		@@ -281,6 +282,18 @@ asmlinkage void do_page_fault(struct pt_regs *regs)
		pte_k = pte_offset_kernel(pmd_k, addr);
		if (!pte_present(*pte_k))
		goto no_context;

		/*
		* The kernel assumes that TLBs don't cache invalid
		* entries, but in RISC-V, SFENCE.VMA specifies an
		* ordering constraint, not a cache flush; it is
		* necessary even after writing invalid entries.
		* Relying on flush_tlb_fix_spurious_fault would
		* suffice, but the extra traps reduce
		* performance. So, eagerly SFENCE.VMA.
		*/
		local_flush_tlb_page(addr);

		return;
		}
		}