Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit a95890b4 authored by Hawking Zhang's avatar Hawking Zhang Committed by Alex Deucher
Browse files

drm/amdgpu: add interface to enable/disable mmhub pg on raven 



Signed-off-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 2fcd43ce

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

+48 −0
Original line number Diff line number Diff line
@@ -414,6 +414,54 @@ void mmhub_v1_0_initialize_power_gating(struct amdgpu_device *adev) 
	WREG32_SOC15(MMHUB, 0, mmPCTL1_MISC, pctl1_misc);

}



void mmhub_v1_0_update_power_gating(struct amdgpu_device *adev,

				bool enable)

{

	uint32_t pctl0_reng_execute = 0;

	uint32_t pctl1_reng_execute = 0;



	if (amdgpu_sriov_vf(adev))

		return;



	pctl0_reng_execute = RREG32_SOC15(MMHUB, 0, mmPCTL0_RENG_EXECUTE);

	pctl1_reng_execute = RREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_EXECUTE);



	if (enable) {

		pctl0_reng_execute = REG_SET_FIELD(pctl0_reng_execute,

						PCTL0_RENG_EXECUTE,

						RENG_EXECUTE_ON_PWR_UP, 1);

		pctl0_reng_execute = REG_SET_FIELD(pctl0_reng_execute,

						PCTL0_RENG_EXECUTE,

						RENG_EXECUTE_ON_REG_UPDATE, 1);

		WREG32_SOC15(MMHUB, 0, mmPCTL0_RENG_EXECUTE, pctl0_reng_execute);



		pctl1_reng_execute = REG_SET_FIELD(pctl1_reng_execute,

						PCTL1_RENG_EXECUTE,

						RENG_EXECUTE_ON_PWR_UP, 1);

		pctl1_reng_execute = REG_SET_FIELD(pctl1_reng_execute,

						PCTL1_RENG_EXECUTE,

						RENG_EXECUTE_ON_REG_UPDATE, 1);

		WREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_EXECUTE, pctl1_reng_execute);



	} else {

		pctl0_reng_execute = REG_SET_FIELD(pctl0_reng_execute,

						PCTL0_RENG_EXECUTE,

						RENG_EXECUTE_ON_PWR_UP, 0);

		pctl0_reng_execute = REG_SET_FIELD(pctl0_reng_execute,

						PCTL0_RENG_EXECUTE,

						RENG_EXECUTE_ON_REG_UPDATE, 0);

		WREG32_SOC15(MMHUB, 0, mmPCTL0_RENG_EXECUTE, pctl0_reng_execute);



		pctl1_reng_execute = REG_SET_FIELD(pctl1_reng_execute,

						PCTL1_RENG_EXECUTE,

						RENG_EXECUTE_ON_PWR_UP, 0);

		pctl1_reng_execute = REG_SET_FIELD(pctl1_reng_execute,

						PCTL1_RENG_EXECUTE,

						RENG_EXECUTE_ON_REG_UPDATE, 0);

		WREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_EXECUTE, pctl1_reng_execute);

	}

}



int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)

{

	if (amdgpu_sriov_vf(adev)) {

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h

+2 −0
Original line number Diff line number Diff line
@@ -33,6 +33,8 @@ int mmhub_v1_0_set_clockgating(struct amdgpu_device *adev, 
			       enum amd_clockgating_state state);

void mmhub_v1_0_get_clockgating(struct amdgpu_device *adev, u32 *flags);

void mmhub_v1_0_initialize_power_gating(struct amdgpu_device *adev);

void mmhub_v1_0_update_power_gating(struct amdgpu_device *adev,

                                bool enable);



extern const struct amd_ip_funcs mmhub_v1_0_ip_funcs;

extern const struct amdgpu_ip_block_version mmhub_v1_0_ip_block;