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Commit a94cf2a6 authored by Sergei Shtylyov's avatar Sergei Shtylyov Committed by David S. Miller
Browse files

sh_eth: fix TSU init on SH7734/R8A7740



It appears that the single port Ether controllers having TSU (like SH7734/
R8A7740) need the same kind of treating in sh_eth_tsu_init() as R7S72100
currently has -- they also don't have the TSU registers related e.g. to
passing the frames between ports. Add the 'sh_eth_cpu_data::dual_port'
flag and use it as a new criterion for taking a "short path" in the TSU
init sequence in order to avoid writing to the non-existent registers...

Fixes: f0e81fec ("net: sh_eth: Add support SH7734")
Fixes: 73a0d907 ("net: sh_eth: add support R8A7740")
Signed-off-by: default avatarSergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Tested-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 4869a147
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+5 −1
Original line number Diff line number Diff line
@@ -752,6 +752,7 @@ static struct sh_eth_cpu_data sh7757_data = {
	.rpadir		= 1,
	.rpadir_value   = 2 << 16,
	.rtrate		= 1,
	.dual_port	= 1,
};

#define SH_GIGA_ETH_BASE	0xfee00000UL
@@ -830,6 +831,7 @@ static struct sh_eth_cpu_data sh7757_data_giga = {
	.no_trimd	= 1,
	.no_ade		= 1,
	.tsu		= 1,
	.dual_port	= 1,
};

/* SH7734 */
@@ -900,6 +902,7 @@ static struct sh_eth_cpu_data sh7763_data = {
	.tsu		= 1,
	.irq_flags	= IRQF_SHARED,
	.magic		= 1,
	.dual_port	= 1,
};

static struct sh_eth_cpu_data sh7619_data = {
@@ -932,6 +935,7 @@ static struct sh_eth_cpu_data sh771x_data = {
			  EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
			  EESIPR_PREIP | EESIPR_CERFIP,
	.tsu		= 1,
	.dual_port	= 1,
};

static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
@@ -2915,7 +2919,7 @@ static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
/* SuperH's TSU register init function */
static void sh_eth_tsu_init(struct sh_eth_private *mdp)
{
	if (sh_eth_is_rz_fast_ether(mdp)) {
	if (!mdp->cd->dual_port) {
		sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
		sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL,
				 TSU_FWSLC);	/* Enable POST registers */
+1 −0
Original line number Diff line number Diff line
@@ -509,6 +509,7 @@ struct sh_eth_cpu_data {
	unsigned rmiimode:1;	/* EtherC has RMIIMODE register */
	unsigned rtrate:1;	/* EtherC has RTRATE register */
	unsigned magic:1;	/* EtherC has ECMR.MPDE and ECSR.MPD */
	unsigned dual_port:1;	/* Dual EtherC/E-DMAC */
};

struct sh_eth_private {