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Commit a8caad66 authored by Gaku Inami's avatar Gaku Inami Committed by Simon Horman
Browse files

ARM: shmobile: Consolidate the pm code for R-Car Gen2 



The pm code for R-Car Gen2 is scatterd in each SoC. These files
(pm-r8a7790.c/pm-r8a7791.c) have some overlap code. This change
consolidate the pm code for R-Car Gen2 into one.

Signed-off-by: default avatarGaku Inami <gaku.inami.xw@bp.renesas.com>
Acked-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
parent 78420b5d

arch/arm/mach-shmobile/Makefile

+3 −2
Original line number Diff line number Diff line
@@ -12,8 +12,8 @@ obj-$(CONFIG_ARCH_R8A73A4) += setup-r8a73a4.o 
obj-$(CONFIG_ARCH_R8A7740)	+= setup-r8a7740.o pm-r8a7740.o

obj-$(CONFIG_ARCH_R8A7778)	+= setup-r8a7778.o

obj-$(CONFIG_ARCH_R8A7779)	+= setup-r8a7779.o pm-r8a7779.o

obj-$(CONFIG_ARCH_R8A7790)	+= setup-r8a7790.o pm-r8a7790.o

obj-$(CONFIG_ARCH_R8A7791)	+= setup-r8a7791.o pm-r8a7791.o

obj-$(CONFIG_ARCH_R8A7790)	+= setup-r8a7790.o

obj-$(CONFIG_ARCH_R8A7791)	+= setup-r8a7791.o

obj-$(CONFIG_ARCH_R8A7794)	+= setup-r8a7794.o

obj-$(CONFIG_ARCH_EMEV2)	+= setup-emev2.o

obj-$(CONFIG_ARCH_R7S72100)	+= setup-r7s72100.o
@@ -50,6 +50,7 @@ obj-$(CONFIG_CPU_IDLE) += cpuidle.o 
obj-$(CONFIG_CPU_FREQ)		+= cpufreq.o

obj-$(CONFIG_PM_RCAR)		+= pm-rcar.o

obj-$(CONFIG_PM_RMOBILE)	+= pm-rmobile.o

obj-$(CONFIG_ARCH_RCAR_GEN2)	+= pm-rcar-gen2.o



# special sh7372 handling for IRQ objects and low level sleep code

obj-$(CONFIG_ARCH_SH7372)	+= entry-intc.o sleep-sh7372.o

arch/arm/mach-shmobile/pm-r8a7790.c

deleted100644 → 0
+0 −82
Original line number Diff line number Diff line 
/*

 * r8a7790 Power management support

 *

 * Copyright (C) 2013  Renesas Electronics Corporation

 * Copyright (C) 2011  Renesas Solutions Corp.

 * Copyright (C) 2011  Magnus Damm

 *

 * This file is subject to the terms and conditions of the GNU General Public

 * License.  See the file "COPYING" in the main directory of this archive

 * for more details.

 */



#include <linux/kernel.h>

#include <linux/smp.h>

#include <asm/io.h>

#include "common.h"

#include "pm-rcar.h"

#include "r8a7790.h"



/* RST */

#define RST		0xe6160000

#define CA15BAR		0x0020

#define CA7BAR		0x0030

#define CA15RESCNT	0x0040

#define CA7RESCNT	0x0044



/* On-chip RAM */

#define MERAM          0xe8080000



/* SYSC */

#define SYSCIER 0x0c

#define SYSCIMR 0x10



#if defined(CONFIG_SMP)



static void __init r8a7790_sysc_init(void)

{

	void __iomem *base = rcar_sysc_init(0xe6180000);



	/* enable all interrupt sources, but do not use interrupt handler */

	iowrite32(0x013111ef, base + SYSCIER);

	iowrite32(0, base + SYSCIMR);

}



#else /* CONFIG_SMP */



static inline void r8a7790_sysc_init(void) {}



#endif /* CONFIG_SMP */



void __init r8a7790_pm_init(void)

{

	void __iomem *p;

	u32 bar;

	static int once;



	if (once++)

		return;



	/* MERAM for jump stub, because BAR requires 256KB aligned address */

	p = ioremap_nocache(MERAM, shmobile_boot_size);

	memcpy_toio(p, shmobile_boot_vector, shmobile_boot_size);

	iounmap(p);



	/* setup reset vectors */

	p = ioremap_nocache(RST, 0x63);

	bar = (MERAM >> 8) & 0xfffffc00;

	writel_relaxed(bar, p + CA15BAR);

	writel_relaxed(bar, p + CA7BAR);

	writel_relaxed(bar | 0x10, p + CA15BAR);

	writel_relaxed(bar | 0x10, p + CA7BAR);



	/* de-assert reset for all CPUs */

	writel_relaxed((readl_relaxed(p + CA15RESCNT) & ~0x0f) | 0xa5a50000,

		       p + CA15RESCNT);

	writel_relaxed((readl_relaxed(p + CA7RESCNT) & ~0x0f) | 0x5a5a0000,

		       p + CA7RESCNT);

	iounmap(p);



	r8a7790_sysc_init();

	shmobile_smp_apmu_suspend_init();

}

arch/arm/mach-shmobile/pm-r8a7791.c→arch/arm/mach-shmobile/pm-rcar-gen2.c

+115 −0
Original line number Diff line number Diff line 
/*

 * r8a7791 Power management support

 * R-Car Generation 2 Power management support

 *

 * Copyright (C) 2014  Renesas Electronics Corporation

 * Copyright (C) 2013 - 2015  Renesas Electronics Corporation

 * Copyright (C) 2011  Renesas Solutions Corp.

 * Copyright (C) 2011  Magnus Damm

 *
@@ -11,15 +11,22 @@ 
 */



#include <linux/kernel.h>

#include <linux/of.h>

#include <linux/smp.h>

#include <asm/io.h>

#include "common.h"

#include "pm-rcar.h"

#include "r8a7791.h"

#include "rcar-gen2.h"



/* RST */

#define RST		0xe6160000

#define CA15BAR		0x0020

#define CA7BAR		0x0030

#define CA15RESCNT	0x0040

#define CA7RESCNT	0x0044



/* On-chip RAM */

#define MERAM		0xe8080000

#define RAM		0xe6300000



/* SYSC */
@@ -28,46 +35,81 @@ 


#if defined(CONFIG_SMP)



static void __init r8a7791_sysc_init(void)

static void __init rcar_gen2_sysc_init(u32 syscier)

{

	void __iomem *base = rcar_sysc_init(0xe6180000);



	/* enable all interrupt sources, but do not use interrupt handler */

	iowrite32(0x00111003, base + SYSCIER);

	iowrite32(syscier, base + SYSCIER);

	iowrite32(0, base + SYSCIMR);

}



#else /* CONFIG_SMP */



static inline void r8a7791_sysc_init(void) {}

static inline void rcar_gen2_sysc_init(u32 syscier) {}



#endif /* CONFIG_SMP */



void __init r8a7791_pm_init(void)

void __init rcar_gen2_pm_init(void)

{

	void __iomem *p;

	u32 bar;

	static int once;

	struct device_node *np, *cpus;

	bool has_a7 = false;

	bool has_a15 = false;

	phys_addr_t boot_vector_addr = 0;

	u32 syscier = 0;



	if (once++)

		return;



	cpus = of_find_node_by_path("/cpus");

	if (!cpus)

		return;



	for_each_child_of_node(cpus, np) {

		if (of_device_is_compatible(np, "arm,cortex-a15"))

			has_a15 = true;

		else if (of_device_is_compatible(np, "arm,cortex-a7"))

			has_a7 = true;

	}



	if (of_machine_is_compatible("renesas,r8a7790")) {

		boot_vector_addr = MERAM;

		syscier = 0x013111ef;



	} else if (of_machine_is_compatible("renesas,r8a7791")) {

		boot_vector_addr = RAM;

		syscier = 0x00111003;

	}



	/* RAM for jump stub, because BAR requires 256KB aligned address */

	p = ioremap_nocache(RAM, shmobile_boot_size);

	p = ioremap_nocache(boot_vector_addr, shmobile_boot_size);

	memcpy_toio(p, shmobile_boot_vector, shmobile_boot_size);

	iounmap(p);



	/* setup reset vectors */

	p = ioremap_nocache(RST, 0x63);

	bar = (RAM >> 8) & 0xfffffc00;

	bar = (boot_vector_addr >> 8) & 0xfffffc00;

	if (has_a15) {

		writel_relaxed(bar, p + CA15BAR);

		writel_relaxed(bar | 0x10, p + CA15BAR);



	/* enable clocks to all CPUs */

	writel_relaxed((readl_relaxed(p + CA15RESCNT) & ~0x0f) | 0xa5a50000,

		       p + CA15RESCNT);

		/* de-assert reset for CA15 CPUs */

		writel_relaxed((readl_relaxed(p + CA15RESCNT) & ~0x0f) |

				0xa5a50000, p + CA15RESCNT);

	}

	if (has_a7) {

		writel_relaxed(bar, p + CA7BAR);

		writel_relaxed(bar | 0x10, p + CA7BAR);



		/* de-assert reset for CA7 CPUs */

		writel_relaxed((readl_relaxed(p + CA7RESCNT) & ~0x0f) |

				0x5a5a0000, p + CA7RESCNT);

	}

	iounmap(p);



	r8a7791_sysc_init();

	rcar_gen2_sysc_init(syscier);

	shmobile_smp_apmu_suspend_init();

}

arch/arm/mach-shmobile/r8a7790.h

+0 −1
Original line number Diff line number Diff line 
#ifndef __ASM_R8A7790_H__

#define __ASM_R8A7790_H__



void r8a7790_pm_init(void);

extern struct smp_operations r8a7790_smp_ops;



#endif /* __ASM_R8A7790_H__ */

arch/arm/mach-shmobile/r8a7791.h

+0 −1
Original line number Diff line number Diff line 
#ifndef __ASM_R8A7791_H__

#define __ASM_R8A7791_H__



void r8a7791_pm_init(void);

extern struct smp_operations r8a7791_smp_ops;



#endif /* __ASM_R8A7791_H__ */