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Commit a8bcb24c authored by Bjorn Helgaas's avatar Bjorn Helgaas Committed by Greg Kroah-Hartman
Browse files

drm/radeon: Replace numbers with PCI_EXP_LNKCTL2 definitions 

[ Upstream commit ca56f99c18cafdeae6961ce9d87fc978506152ca ]

Replace hard-coded magic numbers with the descriptive PCI_EXP_LNKCTL2
definitions.  No functional change intended.

Link: https://lore.kernel.org/r/20191112173503.176611-4-helgaas@kernel.org


Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Stable-dep-of: 7189576e8a82 ("drm/radeon: Use RMW accessors for changing LNKCTL")
Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
parent 69257bb6

drivers/gpu/drm/radeon/cik.c

+14 −8
Original line number Diff line number Diff line
@@ -9615,13 +9615,19 @@ static void cik_pcie_gen3_enable(struct radeon_device *rdev) 


				/* linkctl2 */

				pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16);

				tmp16 &= ~((1 << 4) | (7 << 7));

				tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 7)));

				tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP |

					   PCI_EXP_LNKCTL2_TX_MARGIN);

				tmp16 |= (bridge_cfg2 &

					  (PCI_EXP_LNKCTL2_ENTER_COMP |

					   PCI_EXP_LNKCTL2_TX_MARGIN));

				pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16);



				pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);

				tmp16 &= ~((1 << 4) | (7 << 7));

				tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 7)));

				tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP |

					   PCI_EXP_LNKCTL2_TX_MARGIN);

				tmp16 |= (gpu_cfg2 &

					  (PCI_EXP_LNKCTL2_ENTER_COMP |

					   PCI_EXP_LNKCTL2_TX_MARGIN));

				pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);



				tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
@@ -9637,13 +9643,13 @@ static void cik_pcie_gen3_enable(struct radeon_device *rdev) 
	WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);



	pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);

	tmp16 &= ~0xf;

	tmp16 &= ~PCI_EXP_LNKCTL2_TLS;

	if (speed_cap == PCIE_SPEED_8_0GT)

		tmp16 |= 3; /* gen3 */

		tmp16 |= PCI_EXP_LNKCTL2_TLS_8_0GT; /* gen3 */

	else if (speed_cap == PCIE_SPEED_5_0GT)

		tmp16 |= 2; /* gen2 */

		tmp16 |= PCI_EXP_LNKCTL2_TLS_5_0GT; /* gen2 */

	else

		tmp16 |= 1; /* gen1 */

		tmp16 |= PCI_EXP_LNKCTL2_TLS_2_5GT; /* gen1 */

	pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);



	speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);

drivers/gpu/drm/radeon/si.c

+14 −8
Original line number Diff line number Diff line
@@ -7198,13 +7198,19 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev) 


				/* linkctl2 */

				pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16);

				tmp16 &= ~((1 << 4) | (7 << 7));

				tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 7)));

				tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP |

					   PCI_EXP_LNKCTL2_TX_MARGIN);

				tmp16 |= (bridge_cfg2 &

					  (PCI_EXP_LNKCTL2_ENTER_COMP |

					   PCI_EXP_LNKCTL2_TX_MARGIN));

				pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16);



				pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);

				tmp16 &= ~((1 << 4) | (7 << 7));

				tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 7)));

				tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP |

					   PCI_EXP_LNKCTL2_TX_MARGIN);

				tmp16 |= (gpu_cfg2 &

					  (PCI_EXP_LNKCTL2_ENTER_COMP |

					   PCI_EXP_LNKCTL2_TX_MARGIN));

				pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);



				tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
@@ -7220,13 +7226,13 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev) 
	WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);



	pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);

	tmp16 &= ~0xf;

	tmp16 &= ~PCI_EXP_LNKCTL2_TLS;

	if (speed_cap == PCIE_SPEED_8_0GT)

		tmp16 |= 3; /* gen3 */

		tmp16 |= PCI_EXP_LNKCTL2_TLS_8_0GT; /* gen3 */

	else if (speed_cap == PCIE_SPEED_5_0GT)

		tmp16 |= 2; /* gen2 */

		tmp16 |= PCI_EXP_LNKCTL2_TLS_5_0GT; /* gen2 */

	else

		tmp16 |= 1; /* gen1 */

		tmp16 |= PCI_EXP_LNKCTL2_TLS_2_5GT; /* gen1 */

	pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);



	speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);