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Commit a7d1b3f4 authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Store the pipe pixel rate in the crtc state 



Rather than recomputing the pipe pixel rate on demand everywhere, let's
just stick the precomputed value into the crtc state.

v2: Rebase due to min_pixclk[] code movement
    Document the new pixel_rate struct member (Ander)
    Combine vlv/chv with bdw+ in intel_modeset_readout_hw_state()
v3: Fix typos in commit message (David)

Cc: Ander Conselvan De Oliveira <conselvan2@gmail.com>
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarAnder Conselvan de Oliveira <conselvan2@gmail.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20170126195031.32343-1-ville.syrjala@linux.intel.com
parent fb51ff40

drivers/gpu/drm/i915/intel_display.c

+28 −8
Original line number Diff line number Diff line
@@ -7184,7 +7184,7 @@ static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv, 
	 *

	 * Should measure whether using a lower cdclk w/o IPS

	 */

	return ilk_pipe_pixel_rate(pipe_config) <=

	return pipe_config->pixel_rate <=

		dev_priv->max_cdclk_freq * 95 / 100;

}
@@ -7208,6 +7208,19 @@ static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) 
		(crtc->pipe == PIPE_A || IS_I915G(dev_priv));

}



static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)

{

	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);



	if (HAS_GMCH_DISPLAY(dev_priv))

		/* FIXME calculate proper pipe pixel rate for GMCH pfit */

		crtc_state->pixel_rate =

			crtc_state->base.adjusted_mode.crtc_clock;

	else

		crtc_state->pixel_rate =

			ilk_pipe_pixel_rate(crtc_state);

}



static int intel_crtc_compute_config(struct intel_crtc *crtc,

				     struct intel_crtc_state *pipe_config)

{
@@ -7254,6 +7267,8 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc, 
		adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)

		return -EINVAL;



	intel_crtc_compute_pixel_rate(pipe_config);



	if (HAS_IPS(dev_priv))

		hsw_compute_ips_config(crtc, pipe_config);
@@ -10322,7 +10337,7 @@ static int ilk_max_pixel_rate(struct drm_atomic_state *state) 
			continue;

		}



		pixel_rate = ilk_pipe_pixel_rate(crtc_state);

		pixel_rate = crtc_state->pixel_rate;



		if (IS_BROADWELL(dev_priv) || IS_GEN9(dev_priv))

			pixel_rate = bdw_adjust_min_pipe_pixel_rate(crtc_state,
@@ -12832,9 +12847,10 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc, 
	DRM_DEBUG_KMS("adjusted mode:\n");

	drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);

	intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);

	DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d\n",

	DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d, pixel rate %d\n",

		      pipe_config->port_clock,

		      pipe_config->pipe_src_w, pipe_config->pipe_src_h);

		      pipe_config->pipe_src_w, pipe_config->pipe_src_h,

		      pipe_config->pixel_rate);



	if (INTEL_GEN(dev_priv) >= 9)

		DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
@@ -13410,6 +13426,7 @@ intel_pipe_config_compare(struct drm_i915_private *dev_priv, 
		}



		PIPE_CONF_CHECK_I(scaler_state.scaler_id);

		PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);

	}



	/* BDW+ don't expose a synchronous way to read the state */
@@ -13701,6 +13718,8 @@ verify_crtc_state(struct drm_crtc *crtc, 
		}

	}



	intel_crtc_compute_pixel_rate(pipe_config);



	if (!new_crtc_state->active)

		return;
@@ -17177,10 +17196,11 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev) 
			 */

			crtc_state->base.mode.private_flags = I915_MODE_FLAG_INHERITED;



			if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))

				pixclk = ilk_pipe_pixel_rate(crtc_state);

			else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))

				pixclk = crtc_state->base.adjusted_mode.crtc_clock;

			intel_crtc_compute_pixel_rate(crtc_state);



			if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv) ||

			    IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))

				pixclk = crtc_state->pixel_rate;

			else

				WARN_ON(dev_priv->display.modeset_calc_cdclk);

drivers/gpu/drm/i915/intel_drv.h

+6 −0
Original line number Diff line number Diff line
@@ -544,6 +544,12 @@ struct intel_crtc_state { 
	 * and get clipped at the edges. */

	int pipe_src_w, pipe_src_h;



	/*

	 * Pipe pixel rate, adjusted for

	 * panel fitter/pipe scaler downscaling.

	 */

	unsigned int pixel_rate;



	/* Whether to set up the PCH/FDI. Note that we never allow sharing

	 * between pch encoders and cpu encoders. */

	bool has_pch_encoder;

drivers/gpu/drm/i915/intel_fbc.c

+1 −2
Original line number Diff line number Diff line
@@ -742,8 +742,7 @@ static void intel_fbc_update_state_cache(struct intel_crtc *crtc, 


	cache->crtc.mode_flags = crtc_state->base.adjusted_mode.flags;

	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))

		cache->crtc.hsw_bdw_pixel_rate =

			ilk_pipe_pixel_rate(crtc_state);

		cache->crtc.hsw_bdw_pixel_rate = crtc_state->pixel_rate;



	cache->plane.rotation = plane_state->base.rotation;

	cache->plane.src_w = drm_rect_width(&plane_state->base.src) >> 16;

drivers/gpu/drm/i915/intel_pm.c

+7 −7
Original line number Diff line number Diff line
@@ -1820,12 +1820,12 @@ static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate, 


	cpp = pstate->base.fb->format->cpp[0];



	method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);

	method1 = ilk_wm_method1(cstate->pixel_rate, cpp, mem_value);



	if (!is_lp)

		return method1;



	method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),

	method2 = ilk_wm_method2(cstate->pixel_rate,

				 cstate->base.adjusted_mode.crtc_htotal,

				 drm_rect_width(&pstate->base.dst),

				 cpp, mem_value);
@@ -1849,8 +1849,8 @@ static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate, 


	cpp = pstate->base.fb->format->cpp[0];



	method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);

	method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),

	method1 = ilk_wm_method1(cstate->pixel_rate, cpp, mem_value);

	method2 = ilk_wm_method2(cstate->pixel_rate,

				 cstate->base.adjusted_mode.crtc_htotal,

				 drm_rect_width(&pstate->base.dst),

				 cpp, mem_value);
@@ -1876,7 +1876,7 @@ static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate, 
	if (!cstate->base.active)

		return 0;



	return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),

	return ilk_wm_method2(cstate->pixel_rate,

			      cstate->base.adjusted_mode.crtc_htotal,

			      width, cpp, mem_value);

}
@@ -3559,7 +3559,7 @@ static uint32_t skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cst 
	 * Adjusted plane pixel rate is just the pipe's adjusted pixel rate

	 * with additional adjustments for plane-specific scaling.

	 */

	adjusted_pixel_rate = ilk_pipe_pixel_rate(cstate);

	adjusted_pixel_rate = cstate->pixel_rate;

	downscale_amount = skl_plane_downscale_amount(pstate);



	pixel_rate = adjusted_pixel_rate * downscale_amount >> 16;
@@ -3787,7 +3787,7 @@ skl_compute_linetime_wm(struct intel_crtc_state *cstate) 
	if (!cstate->base.active)

		return 0;



	pixel_rate = ilk_pipe_pixel_rate(cstate);

	pixel_rate = cstate->pixel_rate;



	if (WARN_ON(pixel_rate == 0))

		return 0;