Loading bindings/arm/msm/qcom,llcc.txt +1 −1 Original line number Diff line number Diff line Loading @@ -11,7 +11,7 @@ Properties: - compatible: Usage: required Value type: <string> Definition: must be "qcom,llcc-v1" or "qcom,llcc-v2" Definition: must be "qcom,llcc-v1", "qcom,llcc-v2" or "lagoon-llcc-v1" - reg: Usage: required Loading qcom/lagoon.dtsi +7 −0 Original line number Diff line number Diff line Loading @@ -791,6 +791,13 @@ interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; }; cache-controller@9200000 { compatible = "lagoon-llcc-v1"; reg = <0x9200000 0x50000> , <0x9600000 0x50000>; reg-names = "llcc_base", "llcc_broadcast_base"; cap-based-alloc-and-pwr-collapse; }; qcom,msm-imem@146aa000 { compatible = "qcom,msm-imem"; reg = <0x146aa000 0x1000>; Loading Loading
bindings/arm/msm/qcom,llcc.txt +1 −1 Original line number Diff line number Diff line Loading @@ -11,7 +11,7 @@ Properties: - compatible: Usage: required Value type: <string> Definition: must be "qcom,llcc-v1" or "qcom,llcc-v2" Definition: must be "qcom,llcc-v1", "qcom,llcc-v2" or "lagoon-llcc-v1" - reg: Usage: required Loading
qcom/lagoon.dtsi +7 −0 Original line number Diff line number Diff line Loading @@ -791,6 +791,13 @@ interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; }; cache-controller@9200000 { compatible = "lagoon-llcc-v1"; reg = <0x9200000 0x50000> , <0x9600000 0x50000>; reg-names = "llcc_base", "llcc_broadcast_base"; cap-based-alloc-and-pwr-collapse; }; qcom,msm-imem@146aa000 { compatible = "qcom,msm-imem"; reg = <0x146aa000 0x1000>; Loading