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Commit a77287c0 authored by Archana Sriram's avatar Archana Sriram
Browse files

ARM: dts: qcom: Update bw table and iommu properties of msm8917 GPU 

Following changes are made:

1. Update gpu_bw_tbl in terms of operating point for gpubw.
2. GPU takes care of creating desired dma mapping by itself,
   so disable iommu-dma.
3. Remove unsupported property "qcom,protect".

Change-Id: Ic4330537883d5f639d681cfe7fb63019fb5c26bb
parent c0c998ac

qcom/msm8917-gpu.dtsi

+23 −15
Original line number Diff line number Diff line
@@ -4,26 +4,34 @@ 
		compatible = "qcom,kgsl-busmon";

	};



	gpu_bw_tbl: gpu-bw-tbl {

		compatible = "operating-points-v2";

		opp-0    { opp-hz = /bits/ 64 < 0 >;     }; /* OFF */



		opp-201  { opp-hz = /bits/ 64 < 769 >;   }; /* 1.  201 MHz */



		opp-422  { opp-hz = /bits/ 64 < 1611 >;  }; /* 2.  422 MHz */



		opp-595  { opp-hz = /bits/ 64 < 2270 >;  }; /* 3.  595 MHz */



		opp-768  { opp-hz = /bits/ 64 < 2929 >;  }; /* 4.  768 MHz */



		opp-1113 { opp-hz = /bits/ 64 < 4248 >;  }; /* 5. 1113 MHz */



		opp-1190 { opp-hz = /bits/ 64 < 4541 >;  }; /* 6. 1190 MHz */



		opp-1344 { opp-hz = /bits/ 64 < 5126 >;  }; /* 7. 1344 MHz */



		opp-1478 { opp-hz = /bits/ 64 < 5639 >;  }; /* 8. 1478 MHz */

	};



	/* Bus governor */

	gpubw: qcom,gpubw {

		compatible = "qcom,devbw";

		governor = "bw_vbif";

		qcom,src-dst-ports = <26 512>;

		/*

		 * Need to configure 2x Clock as BIMC

		 * Internally Divides by 2 for Gen1 DDR PHY.

		 */

		operating-points-v2 = <&gpu_bw_tbl>;

		qcom,active-only;

		qcom,bw-tbl =

			< 0 >,    /* Off */

			< 769 >,  /* 1. DDR:100.80 MHz BIMC: 201.60 MHz */

			< 1611 >, /* 2. DDR:211.20 MHz BIMC: 422.40 MHz */

			< 2270 >, /* 3. DDR:297.60 MHz BIMC: 595.20 MHz */

			< 2929 >, /* 4. DDR:384.00 MHz BIMC: 768.00 MHz */

			< 4248 >, /* 5. DDR:556.80 MHz BIMC: 1113.60 MHz */

			< 4541 >, /* 6. DDR:595.20 MHz BIMC: 1190.40 MHz */

			< 5126 >, /* 7. DDR:672.00 MHz BIMC: 1344.00 MHz */

			< 5639 >; /* 8. DDR:739.20 MHz BIMC: 1478.40 MHz */

	};



	msm_gpu: qcom,kgsl-3d0@1c00000 {
@@ -158,7 +166,6 @@ 
		 * The gpu can only program a single context bank

		 * at this fixed offset.

		 */

		qcom,protect = <0xa000 0x1000>;

		clocks = <&gcc GCC_SMMU_CFG_CLK>,

			<&gcc GCC_GFX_TCU_CLK>,

			<&gcc GCC_GTCU_AHB_CLK>,
@@ -169,6 +176,7 @@ 
		gfx3d_user: gfx3d_user {

			compatible = "qcom,smmu-kgsl-cb";

			iommus = <&gfx_iommu 0>;

			qcom,iommu-dma = "disabled";

			qcom,gpu-offset = <0xa000>;

		};

	};