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Commit a74c52de authored by Peter Ujfalusi's avatar Peter Ujfalusi Committed by Mike Turquette
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clk: ti: clk-7xx: Correct ABE DPLL configuration 



ABE DPLL frequency need to be lowered from 361267200
to 180633600 to facilitate the ATL requironments.
The dpll_abe_m2x2_ck clock need to be set to double
of ABE DPLL rate in order to have correct clocks
for audio.

Signed-off-by: default avatarPeter Ujfalusi <peter.ujfalusi@ti.com>
Acked-by: default avatarTero Kristo <t-kristo@ti.com>
Signed-off-by: default avatarMike Turquette <mturquette@linaro.org>
parent 64aa90f2

drivers/clk/ti/clk-7xx.c

+6 −1
Original line number Diff line number Diff line
@@ -16,7 +16,7 @@ 
#include <linux/clkdev.h>

#include <linux/clk/ti.h>



#define DRA7_DPLL_ABE_DEFFREQ				361267200

#define DRA7_DPLL_ABE_DEFFREQ				180633600

#define DRA7_DPLL_GMAC_DEFFREQ				1000000000
@@ -322,6 +322,11 @@ int __init dra7xx_dt_clk_init(void) 
	if (rc)

		pr_err("%s: failed to configure ABE DPLL!\n", __func__);



	dpll_ck = clk_get_sys(NULL, "dpll_abe_m2x2_ck");

	rc = clk_set_rate(dpll_ck, DRA7_DPLL_ABE_DEFFREQ * 2);

	if (rc)

		pr_err("%s: failed to configure ABE DPLL m2x2!\n", __func__);



	dpll_ck = clk_get_sys(NULL, "dpll_gmac_ck");

	rc = clk_set_rate(dpll_ck, DRA7_DPLL_GMAC_DEFFREQ);

	if (rc)