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Commit a73afecb authored by Yicong Yang's avatar Yicong Yang Committed by Greg Kroah-Hartman
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PCI/ASPM: Clear the correct bits when enabling L1 substates 

commit 58a3862a10a317a81097ab0c78aecebabb1704f5 upstream.

In pcie_config_aspm_l1ss(), we cleared the wrong bits when enabling ASPM L1
Substates.  Instead of the L1.x enable bits (PCI_L1SS_CTL1_L1SS_MASK, 0xf), we
cleared the Link Activation Interrupt Enable bit (PCI_L1SS_CAP_L1_PM_SS,
0x10).

Clear the L1.x enable bits before writing the new L1.x configuration.

[bhelgaas: changelog]
Fixes: aeda9ade ("PCI/ASPM: Configure L1 substate settings")
Link: https://lore.kernel.org/r/1584093227-1292-1-git-send-email-yangyicong@hisilicon.com


Signed-off-by: default avatarYicong Yang <yangyicong@hisilicon.com>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
CC: stable@vger.kernel.org	# v4.11+
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 1ada617e

drivers/pci/pcie/aspm.c

+2 −2
Original line number Diff line number Diff line
@@ -747,9 +747,9 @@ static void pcie_config_aspm_l1ss(struct pcie_link_state *link, u32 state) 


	/* Enable what we need to enable */

	pci_clear_and_set_dword(parent, up_cap_ptr + PCI_L1SS_CTL1,

				PCI_L1SS_CAP_L1_PM_SS, val);

				PCI_L1SS_CTL1_L1SS_MASK, val);

	pci_clear_and_set_dword(child, dw_cap_ptr + PCI_L1SS_CTL1,

				PCI_L1SS_CAP_L1_PM_SS, val);

				PCI_L1SS_CTL1_L1SS_MASK, val);

}



static void pcie_config_aspm_dev(struct pci_dev *pdev, u32 val)