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Commit a6c0d1fd authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Added disable state for i3c GPIO"

parents 47f85f04 e5e715da

qcom/kona-pinctrl.dtsi

+26 −0
Original line number Diff line number Diff line
@@ -3205,6 +3205,19 @@ 
					bias-pull-up;

				};

			};



			qupv3_se0_i3c_disable: qupv3_se0_i3c_disable {

				mux {

					pins = "gpio28", "gpio29";

					function = "gpio";

				};



				config {

					pins = "gpio28", "gpio29";

					drive-strength = <2>;

					bias-pull-down;

				};

			};

		};



		/* QUPv3_0 North SE1 mappings */
@@ -3234,6 +3247,19 @@ 
					bias-pull-up;

				};

			};



			qupv3_se1_i3c_disable: qupv3_se1_i3c_disable {

				mux {

					pins = "gpio4", "gpio5";

					function = "gpio";

				};



				config {

					pins = "gpio4", "gpio5";

					drive-strength = <2>;

					bias-pull-down;

				};

			};

		};



		/* SE 0 pin mappings */

qcom/kona-qupv3.dtsi

+4 −2
Original line number Diff line number Diff line
@@ -21,9 +21,10 @@ 
		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>,

			<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,

			<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-names = "default", "sleep", "disable";

		pinctrl-0 = <&qupv3_se0_i3c_active>;

		pinctrl-1 = <&qupv3_se0_i3c_sleep>;

		pinctrl-2 = <&qupv3_se0_i3c_disable>;

		interrupts-extended = <&intc GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>,

				<&pdc 31 IRQ_TYPE_LEVEL_HIGH>,

				<&pdc 30 IRQ_TYPE_LEVEL_HIGH>;
@@ -44,9 +45,10 @@ 
		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S1_CLK>,

			<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,

			<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-names = "default", "sleep", "disable";

		pinctrl-0 = <&qupv3_se1_i3c_active>;

		pinctrl-1 = <&qupv3_se1_i3c_sleep>;

		pinctrl-2 = <&qupv3_se1_i3c_disable>;

		interrupts-extended = <&intc GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>,

				<&pdc 33 IRQ_TYPE_LEVEL_HIGH>,

				<&pdc 32 IRQ_TYPE_LEVEL_HIGH>;