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Commit a6a63ac0 authored by Harry Yang's avatar Harry Yang
Browse files

power: smb5-lib: unify wdog timer for SW step-charging 



Currently, SW Step charging is periodically evaluated on different wdog
timers, with some targets on bark for every 16s and others on snarl for
8s.

However, recent charger SW optimization for wakeups requires 8s timeout,
which is for all targets.

Update with snarl 8s timer for all.

Change-Id: Ie29d836298b8a9b799ee082386c3051c70e1ff6d
Signed-off-by: default avatarHarry Yang <harryy@codeaurora.org>
parent 2ff59c37

drivers/power/supply/qcom/qpnp-smb5.c

+4 −23
Original line number Diff line number Diff line
@@ -428,6 +428,7 @@ static int smb5_configure_internal_pull(struct smb_charger *chg, int type, 
#define MICRO_3PA			3000000

#define OTG_DEFAULT_DEGLITCH_TIME_MS	50

#define DEFAULT_WD_BARK_TIME		64

#define DEFAULT_WD_SNARL_TIME_8S	0x07

static int smb5_parse_dt_misc(struct smb5 *chip, struct device_node *node)

{

	int rc = 0, byte_len;
@@ -465,7 +466,7 @@ static int smb5_parse_dt_misc(struct smb5 *chip, struct device_node *node) 
	rc = of_property_read_u32(node, "qcom,wd-snarl-time-config",

					&chip->dt.wd_snarl_time_cfg);

	if (rc < 0)

		chip->dt.wd_snarl_time_cfg = -EINVAL;

		chip->dt.wd_snarl_time_cfg = DEFAULT_WD_SNARL_TIME_8S;



	chip->dt.no_battery = of_property_read_bool(node,

						"qcom,batteryless-platform");
@@ -2595,10 +2596,6 @@ static int smb5_init_hw(struct smb5 *chip) 
	val = (ilog2(chip->dt.wd_bark_time / 16) << BARK_WDOG_TIMEOUT_SHIFT)

			& BARK_WDOG_TIMEOUT_MASK;

	val |= (BITE_WDOG_TIMEOUT_8S | BITE_WDOG_DISABLE_CHARGING_CFG_BIT);



	if (chip->dt.wd_snarl_time_cfg == -EINVAL)

		val |= SNARL_WDOG_TMOUT_8S;

	else

	val |= (chip->dt.wd_snarl_time_cfg << SNARL_WDOG_TIMEOUT_SHIFT)

			& SNARL_WDOG_TIMEOUT_MASK;
@@ -2612,11 +2609,8 @@ static int smb5_init_hw(struct smb5 *chip) 
		return rc;

	}



	val = WDOG_TIMER_EN_ON_PLUGIN_BIT;

	if (chip->dt.wd_snarl_time_cfg == -EINVAL)

		val |= BARK_WDOG_INT_EN_BIT;



	/* enable WD BARK and enable it on plugin */

	val = WDOG_TIMER_EN_ON_PLUGIN_BIT | BARK_WDOG_INT_EN_BIT;

	rc = smblib_masked_write(chg, WD_CFG_REG,

			WATCHDOG_TRIGGER_AFP_EN_BIT |

			WDOG_TIMER_EN_ON_PLUGIN_BIT |
@@ -3116,19 +3110,6 @@ static int smb5_request_interrupts(struct smb5 *chip) 
		}

	}



	/*

	 * WDOG_SNARL_IRQ is required for SW Thermal Regulation WA. In case

	 * the WA is not required and neither is the snarl timer configuration

	 * defined, disable the WDOG_SNARL_IRQ to prevent interrupt storm.

	 */



	if (chg->irq_info[WDOG_SNARL_IRQ].irq && (!(chg->wa_flags &

				SW_THERM_REGULATION_WA) &&

				chip->dt.wd_snarl_time_cfg == -EINVAL)) {

		disable_irq_wake(chg->irq_info[WDOG_SNARL_IRQ].irq);

		disable_irq_nosync(chg->irq_info[WDOG_SNARL_IRQ].irq);

	}



	vote(chg->limited_irq_disable_votable, CHARGER_TYPE_VOTER, true, 0);

	vote(chg->hdc_irq_disable_votable, CHARGER_TYPE_VOTER, true, 0);

drivers/power/supply/qcom/smb5-lib.c

+0 −3
Original line number Diff line number Diff line
@@ -6209,9 +6209,6 @@ irqreturn_t wdog_bark_irq_handler(int irq, void *data) 
	if (rc < 0)

		smblib_err(chg, "Couldn't pet the dog rc=%d\n", rc);



	if (chg->step_chg_enabled)

		power_supply_changed(chg->batt_psy);



	return IRQ_HANDLED;

}