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Commit a6589b44 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'reset-for-4.11' of git://git.pengutronix.de/pza/linux into next/drivers 

Reset controller changes for v4.11

- fix ti_syscon reset_status reporting
- add Hisilicon Hi3660 reset controller driver
- add ZTE ZX2967 reset controller driver
- add LD11 SD-reset block to uniphier reset controller driver
- typo and correctness fixes
- make reset_control_get variants return NULL instead of an
  error for optional, not specified resets and have the other
  reset API functions silently ignore rstc == NULL parameters.

* tag 'reset-for-4.11' of git://git.pengutronix.de/pza/linux

:
  reset: make optional functions really optional
  reset: Change shared flag from int to bool
  reset: uniphier: add compatible string for LD11 SD-reset block
  reset: zx2967: add reset controller driver for ZTE's zx2967 family
  MAINTAINERS: add zx2967 reset controller driver to ARM ZTE architecture
  dt: bindings: add documentation for zx2967 family reset controller
  Documentation: dt: reset: Revise typos in TI syscon reset example
  reset: constify reset_control_ops structures
  reset: hisilicon: add reset-hi3660
  dt-bindings: Document the hi3660 reset bindings
  reset: ti_syscon: fix a ti_syscon_reset_status issue

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 0ff6454b bb475230

Documentation/devicetree/bindings/reset/hisilicon,hi3660-reset.txt

0 → 100644
+43 −0
Original line number Diff line number Diff line 
Hisilicon System Reset Controller

======================================



Please also refer to reset.txt in this directory for common reset

controller binding usage.



The reset controller registers are part of the system-ctl block on

hi3660 SoC.



Required properties:

- compatible: should be

		 "hisilicon,hi3660-reset"

- hisi,rst-syscon: phandle of the reset's syscon.

- #reset-cells : Specifies the number of cells needed to encode a

  reset source.  The type shall be a <u32> and the value shall be 2.



	 Cell #1 : offset of the reset assert control

	           register from the syscon register base

		   offset + 4: deassert control register

		   offset + 8: status control register

	 Cell #2 : bit position of the reset in the reset control register



Example:

	iomcu: iomcu@ffd7e000 {

		compatible = "hisilicon,hi3660-iomcu", "syscon";

		reg = <0x0 0xffd7e000 0x0 0x1000>;

	};



	iomcu_rst: iomcu_rst_controller {

		compatible = "hisilicon,hi3660-reset";

		hisi,rst-syscon = <&iomcu>;

		#reset-cells = <2>;

	};



Specifying reset lines connected to IP modules

==============================================

example:



        i2c0: i2c@..... {

                ...

		resets = <&iomcu_rst 0x20 3>; /* offset: 0x20; bit: 3 */

                ...

        };

Documentation/devicetree/bindings/reset/ti-syscon-reset.txt

+4 −4
Original line number Diff line number Diff line
@@ -63,7 +63,7 @@ Example: 
--------

The following example demonstrates a syscon node, the reset controller node

using the syscon node, and a consumer (a DSP device) on the TI Keystone 2

Edison SoC.

66AK2E SoC.



/ {

	soc {
@@ -71,13 +71,13 @@ Edison SoC. 
			compatible = "syscon", "simple-mfd";

			reg = <0x02350000 0x1000>;



			pscrst: psc-reset {

			pscrst: reset-controller {

				compatible = "ti,k2e-pscrst", "ti,syscon-reset";

				#reset-cells = <1>;



				ti,reset-bits = <

					0xa3c 8 0xa3c 8 0x83c 8 (ASSERT_SET|DEASSERT_CLEAR|STATUS_SET)   /* 0: pcrst-dsp0 */

					0xa40 5 0xa44 3 0     0 (ASSERT_SET|DEASSERT_CLEAR|STATUS_NONE)  /* 1: pcrst-example */

					0xa3c 8 0xa3c 8 0x83c 8 (ASSERT_CLEAR | DEASSERT_SET   | STATUS_CLEAR) /* 0: dsp0 */

					0xa40 5 0xa44 3 0     0 (ASSERT_SET   | DEASSERT_CLEAR | STATUS_NONE)  /* 1: example */

				>;

			};

		};

Documentation/devicetree/bindings/reset/uniphier-reset.txt

+24 −23
Original line number Diff line number Diff line
@@ -6,14 +6,14 @@ System reset 


Required properties:

- compatible: should be one of the following:

    "socionext,uniphier-sld3-reset" - for sLD3 SoC.

    "socionext,uniphier-ld4-reset"  - for LD4 SoC.

    "socionext,uniphier-pro4-reset" - for Pro4 SoC.

    "socionext,uniphier-sld8-reset" - for sLD8 SoC.

    "socionext,uniphier-pro5-reset" - for Pro5 SoC.

    "socionext,uniphier-pxs2-reset" - for PXs2/LD6b SoC.

    "socionext,uniphier-ld11-reset" - for LD11 SoC.

    "socionext,uniphier-ld20-reset" - for LD20 SoC.

    "socionext,uniphier-sld3-reset" - for sLD3 SoC

    "socionext,uniphier-ld4-reset"  - for LD4 SoC

    "socionext,uniphier-pro4-reset" - for Pro4 SoC

    "socionext,uniphier-sld8-reset" - for sLD8 SoC

    "socionext,uniphier-pro5-reset" - for Pro5 SoC

    "socionext,uniphier-pxs2-reset" - for PXs2/LD6b SoC

    "socionext,uniphier-ld11-reset" - for LD11 SoC

    "socionext,uniphier-ld20-reset" - for LD20 SoC

- #reset-cells: should be 1.



Example:
@@ -37,14 +37,15 @@ Media I/O (MIO) reset, SD reset 


Required properties:

- compatible: should be one of the following:

    "socionext,uniphier-sld3-mio-reset" - for sLD3 SoC.

    "socionext,uniphier-ld4-mio-reset"  - for LD4 SoC.

    "socionext,uniphier-pro4-mio-reset" - for Pro4 SoC.

    "socionext,uniphier-sld8-mio-reset" - for sLD8 SoC.

    "socionext,uniphier-pro5-sd-reset"  - for Pro5 SoC.

    "socionext,uniphier-pxs2-sd-reset"  - for PXs2/LD6b SoC.

    "socionext,uniphier-ld11-mio-reset" - for LD11 SoC.

    "socionext,uniphier-ld20-sd-reset"  - for LD20 SoC.

    "socionext,uniphier-sld3-mio-reset" - for sLD3 SoC

    "socionext,uniphier-ld4-mio-reset"  - for LD4 SoC

    "socionext,uniphier-pro4-mio-reset" - for Pro4 SoC

    "socionext,uniphier-sld8-mio-reset" - for sLD8 SoC

    "socionext,uniphier-pro5-sd-reset"  - for Pro5 SoC

    "socionext,uniphier-pxs2-sd-reset"  - for PXs2/LD6b SoC

    "socionext,uniphier-ld11-mio-reset" - for LD11 SoC (MIO)

    "socionext,uniphier-ld11-sd-reset"  - for LD11 SoC (SD)

    "socionext,uniphier-ld20-sd-reset"  - for LD20 SoC

- #reset-cells: should be 1.



Example:
@@ -68,13 +69,13 @@ Peripheral reset 


Required properties:

- compatible: should be one of the following:

    "socionext,uniphier-ld4-peri-reset"  - for LD4 SoC.

    "socionext,uniphier-pro4-peri-reset" - for Pro4 SoC.

    "socionext,uniphier-sld8-peri-reset" - for sLD8 SoC.

    "socionext,uniphier-pro5-peri-reset" - for Pro5 SoC.

    "socionext,uniphier-pxs2-peri-reset" - for PXs2/LD6b SoC.

    "socionext,uniphier-ld11-peri-reset" - for LD11 SoC.

    "socionext,uniphier-ld20-peri-reset" - for LD20 SoC.

    "socionext,uniphier-ld4-peri-reset"  - for LD4 SoC

    "socionext,uniphier-pro4-peri-reset" - for Pro4 SoC

    "socionext,uniphier-sld8-peri-reset" - for sLD8 SoC

    "socionext,uniphier-pro5-peri-reset" - for Pro5 SoC

    "socionext,uniphier-pxs2-peri-reset" - for PXs2/LD6b SoC

    "socionext,uniphier-ld11-peri-reset" - for LD11 SoC

    "socionext,uniphier-ld20-peri-reset" - for LD20 SoC

- #reset-cells: should be 1.



Example:

Documentation/devicetree/bindings/reset/zte,zx2967-reset.txt

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+20 −0
Original line number Diff line number Diff line 
ZTE zx2967 SoCs Reset Controller

=======================================



Please also refer to reset.txt in this directory for common reset

controller binding usage.



Required properties:

- compatible: should be one of the following.

	* zte,zx296718-reset

- reg: physical base address of the controller and length of memory mapped

	region.

- #reset-cells: must be 1.



example:



	reset: reset-controller@1461060 {

		compatible = "zte,zx296718-reset";

		reg = <0x01461060 0x8>;

		#reset-cells = <1>;

	};

MAINTAINERS

+2 −0
Original line number Diff line number Diff line
@@ -1985,8 +1985,10 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) 
S:	Maintained

F:	arch/arm/mach-zx/

F:	drivers/clk/zte/

F:	drivers/reset/reset-zx2967.c

F:	Documentation/devicetree/bindings/arm/zte.txt

F:	Documentation/devicetree/bindings/clock/zx296702-clk.txt

F:	Documentation/devicetree/bindings/reset/zte,zx2967-reset.txt



ARM/ZYNQ ARCHITECTURE

M:	Michal Simek <michal.simek@xilinx.com>