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Commit a639e568 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: changes to support dp on lito"

parents 1cf68850 d8fa6335

qcom/kona-sde-pll.dtsi

+8 −2
Original line number Diff line number Diff line
@@ -66,10 +66,16 @@ 
		reg = <0x088ea000 0x200>,

		      <0x088eaa00 0x200>,

		      <0x088ea200 0x200>,

		      <0x088ea2b8 0x8>,

		      <0x088ea2e8 0x4>,

		      <0x088ea600 0x200>,

		      <0x088ea6b8 0x8>,

		      <0x088ea6e8 0x4>,

		      <0xaf03000 0x8>;

		reg-names = "pll_base", "phy_base", "ln_tx0_base",

			"ln_tx1_base", "gdsc_base";

		reg-names = "pll_base", "phy_base",

			"ln_tx0_base", "ln_tx0_tran_base", "ln_tx0_vmode_base",

			"ln_tx1_base", "ln_tx1_tran_base", "ln_tx1_vmode_base",

			"gdsc_base";



		clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>,

			<&clock_rpmh RPMH_CXO_CLK>,

qcom/lito-sde-pll.dtsi

+9 −3
Original line number Diff line number Diff line
@@ -57,7 +57,7 @@ 
		};

	};

	 mdss_dp_pll: qcom,mdss_dp_pll@c011000 {

		compatible = "qcom,mdss_dp_pll_7nm";

		compatible = "qcom,mdss_dp_pll_7nm_v2";

		label = "MDSS DP PLL";

		cell-index = <0>;

		#clock-cells = <1>;
@@ -65,10 +65,16 @@ 
		reg =   <0x088ea000 0x200>,

			<0x088eaa00 0x200>,

			<0x088ea200 0x200>,

			<0x088ea2c0 0x8>,

			<0x088ea2c8 0x4>,

			<0x088ea600 0x200>,

			<0x088ea6c0 0x8>,

			<0x088ea6c8 0x4>,

			<0xaf03000 0x8>;

		reg-names = "pll_base", "phy_base", "ln_tx0_base",

			"ln_tx1_base", "gdsc_base";

		reg-names = "pll_base", "phy_base",

			"ln_tx0_base", "ln_tx0_tran_base", "ln_tx0_vmode_base",

			"ln_tx1_base", "ln_tx1_tran_base", "ln_tx0_vmode_base",

			"gdsc_base";



		clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,

			<&rpmhcc RPMH_CXO_CLK>,