Merge tag 'phy-for-4.12' of...

Required properties (controller (parent) node):

Required properties (controller (parent) node):

 - compatible	: should be one of

 - compatible	: should be one of

		  "mediatek,mt2701-u3phy"

		  "mediatek,mt2701-u3phy"

		  "mediatek,mt2712-u3phy"

		  "mediatek,mt8173-u3phy"

		  "mediatek,mt8173-u3phy"

 - reg		: offset and length of register for phy, exclude port's

 - clocks	: (deprecated, use port's clocks instead) a list of phandle +

		  register.

		  clock-specifier pairs, one for each entry in clock-names

 - clocks	: a list of phandle + clock-specifier pairs, one for each

 - clock-names	: (deprecated, use port's one instead) must contain

		  entry in clock-names

 - clock-names	: must contain

		  "u3phya_ref": for reference clock of usb3.0 analog phy.

		  "u3phya_ref": for reference clock of usb3.0 analog phy.

Required nodes	: a sub-node is required for each port the controller

Required nodes	: a sub-node is required for each port the controller

		  'reg' property is used inside these nodes to describe

		  'reg' property is used inside these nodes to describe

		  the controller's topology.

		  the controller's topology.

Optional properties (controller (parent) node):

 - reg		: offset and length of register shared by multiple ports,

		  exclude port's private register. It is needed on mt2701

		  and mt8173, but not on mt2712.

Required properties (port (child) node):

Required properties (port (child) node):

- reg		: address and length of the register set for the port.

- reg		: address and length of the register set for the port.

- clocks	: a list of phandle + clock-specifier pairs, one for each

		  entry in clock-names

- clock-names	: must contain

		  "ref": 48M reference clock for HighSpeed analog phy; and 26M

			reference clock for SuperSpeed analog phy, sometimes is

			24M, 25M or 27M, depended on platform.

- #phy-cells	: should be 1 (See second example)

- #phy-cells	: should be 1 (See second example)

		  cell after port phandle is phy type from:

		  cell after port phandle is phy type from:

			- PHY_TYPE_USB2

			- PHY_TYPE_USB2

u3phy: usb-phy@11290000 {

u3phy: usb-phy@11290000 {

	compatible = "mediatek,mt8173-u3phy";

	compatible = "mediatek,mt8173-u3phy";

	reg = <0 0x11290000 0 0x800>;

	reg = <0 0x11290000 0 0x800>;

	clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;

	clock-names = "u3phya_ref";

	#address-cells = <2>;

	#address-cells = <2>;

	#size-cells = <2>;

	#size-cells = <2>;

	ranges;

	ranges;

	status = "okay";

	status = "okay";

	phy_port0: port@11290800 {

	u2port0: usb-phy@11290800 {

		reg = <0 0x11290800 0 0x800>;

		reg = <0 0x11290800 0 0x100>;

		clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;

		clock-names = "ref";

		#phy-cells = <1>;

		status = "okay";

	};

	u3port0: usb-phy@11290900 {

		reg = <0 0x11290800 0 0x700>;

		clocks = <&clk26m>;

		clock-names = "ref";

		#phy-cells = <1>;

		#phy-cells = <1>;

		status = "okay";

		status = "okay";

	};

	};

	phy_port1: port@11291000 {

	u2port1: usb-phy@11291000 {

		reg = <0 0x11291000 0 0x800>;

		reg = <0 0x11291000 0 0x100>;

		clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;

		clock-names = "ref";

		#phy-cells = <1>;

		#phy-cells = <1>;

		status = "okay";

		status = "okay";

	};

	};

usb30: usb@11270000 {

usb30: usb@11270000 {

	...

	...

	phys = <&phy_port0 PHY_TYPE_USB3>;

	phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;

	phy-names = "usb3-0";

	phy-names = "usb2-0", "usb3-0";

	...

	...

};

};

Layout differences of banks between mt8173/mt2701 and mt2712

-------------------------------------------------------------

mt8173 and mt2701:

port        offset    bank

shared      0x0000    SPLLC

            0x0100    FMREG

u2 port0    0x0800    U2PHY_COM

u3 port0    0x0900    U3PHYD

            0x0a00    U3PHYD_BANK2

            0x0b00    U3PHYA

            0x0c00    U3PHYA_DA

u2 port1    0x1000    U2PHY_COM

u3 port1    0x1100    U3PHYD

            0x1200    U3PHYD_BANK2

            0x1300    U3PHYA

            0x1400    U3PHYA_DA

u2 port2    0x1800    U2PHY_COM

            ...

mt2712:

port        offset    bank

u2 port0    0x0000    MISC

            0x0100    FMREG

            0x0300    U2PHY_COM

u3 port0    0x0700    SPLLC

            0x0800    CHIP

            0x0900    U3PHYD

            0x0a00    U3PHYD_BANK2

            0x0b00    U3PHYA

            0x0c00    U3PHYA_DA

u2 port1    0x1000    MISC

            0x1100    FMREG

            0x1300    U2PHY_COM

u3 port1    0x1700    SPLLC

            0x1800    CHIP

            0x1900    U3PHYD

            0x1a00    U3PHYD_BANK2

            0x1b00    U3PHYA

            0x1c00    U3PHYA_DA

u2 port2    0x2000    MISC

            ...

    SPLLC shared by u3 ports and FMREG shared by u2 ports on

mt8173/mt2701 are put back into each port; a new bank MISC for

u2 ports and CHIP for u3 ports are added on mt2712.

Required properties (phy (parent) node):

Required properties (phy (parent) node):

 - compatible : should be one of the listed compatibles:

 - compatible : should be one of the listed compatibles:

	* "rockchip,rk3328-usb2phy"

	* "rockchip,rk3366-usb2phy"

	* "rockchip,rk3366-usb2phy"

	* "rockchip,rk3399-usb2phy"

	* "rockchip,rk3399-usb2phy"

 - reg : the address offset of grf for usb-phy configuration.

 - reg : the address offset of grf for usb-phy configuration.

Optional properties:

Optional properties:

 - clocks : phandle + phy specifier pair, for the input clock of phy.

 - clocks : phandle + phy specifier pair, for the input clock of phy.

 - clock-names : input clock name of phy, must be "phyclk".

 - clock-names : input clock name of phy, must be "phyclk".

 - assigned-clocks : phandle of usb 480m clock.

 - assigned-clock-parents : parent of usb 480m clock, select between

		 usb-phy output 480m and xin24m.

		 Refer to clk/clock-bindings.txt for generic clock

		 consumer properties.

Required nodes : a sub-node is required for each port the phy provides.

Required nodes : a sub-node is required for each port the phy provides.

		 The sub-node name is used to identify host or otg port,

		 The sub-node name is used to identify host or otg port,

Qualcomm QMP PHY controller

===========================

QMP phy controller supports physical layer functionality for a number of

controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.

Required properties:

 - compatible: compatible list, contains:

	       "qcom,msm8996-qmp-pcie-phy" for 14nm PCIe phy on msm8996,

	       "qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996.

 - reg: offset and length of register set for PHY's common serdes block.

 - #clock-cells: must be 1

    - Phy pll outputs a bunch of clocks for Tx, Rx and Pipe

      interface (for pipe based PHYs). These clock are then gate-controlled

      by gcc.

 - #address-cells: must be 1

 - #size-cells: must be 1

 - ranges: must be present

 - clocks: a list of phandles and clock-specifier pairs,

	   one for each entry in clock-names.

 - clock-names: "cfg_ahb" for phy config clock,

		"aux" for phy aux clock,

		"ref" for 19.2 MHz ref clk,

		For "qcom,msm8996-qmp-pcie-phy" must contain:

			"aux", "cfg_ahb", "ref".

		For "qcom,msm8996-qmp-usb3-phy" must contain:

			"aux", "cfg_ahb", "ref".

 - resets: a list of phandles and reset controller specifier pairs,

	   one for each entry in reset-names.

 - reset-names: "phy" for reset of phy block,

		"common" for phy common block reset,

		"cfg" for phy's ahb cfg block reset (Optional).

		For "qcom,msm8996-qmp-pcie-phy" must contain:

		 "phy", "common", "cfg".

		For "qcom,msm8996-qmp-usb3-phy" must contain

		 "phy", "common".

 - vdda-phy-supply: Phandle to a regulator supply to PHY core block.

 - vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll block.

Optional properties:

 - vddp-ref-clk-supply: Phandle to a regulator supply to any specific refclk

			pll block.

Required nodes:

 - Each device node of QMP phy is required to have as many child nodes as

   the number of lanes the PHY has.

Required properties for child node:

 - reg: list of offset and length pairs of register sets for PHY blocks -

	tx, rx and pcs.

 - #phy-cells: must be 0

 - clocks: a list of phandles and clock-specifier pairs,

	   one for each entry in clock-names.

 - clock-names: Must contain following for pcie and usb qmp phys:

		 "pipe<lane-number>" for pipe clock specific to each lane.

 - resets: a list of phandles and reset controller specifier pairs,

	   one for each entry in reset-names.

 - reset-names: Must contain following for pcie qmp phys:

		 "lane<lane-number>" for reset specific to each lane.

Example:

	phy@34000 {

		compatible = "qcom,msm8996-qmp-pcie-phy";

		reg = <0x34000 0x488>;

		#clock-cells = <1>;

		#address-cells = <1>;

		#size-cells = <1>;

		ranges;

		clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,

			<&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,

			<&gcc GCC_PCIE_CLKREF_CLK>;

		clock-names = "aux", "cfg_ahb", "ref";

		vdda-phy-supply = <&pm8994_l28>;

		vdda-pll-supply = <&pm8994_l12>;

		resets = <&gcc GCC_PCIE_PHY_BCR>,

			<&gcc GCC_PCIE_PHY_COM_BCR>,

			<&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;

		reset-names = "phy", "common", "cfg";

		pciephy_0: lane@35000 {

			reg = <0x35000 0x130>,

				<0x35200 0x200>,

				<0x35400 0x1dc>;

			#phy-cells = <0>;

			clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;

			clock-names = "pipe0";

			resets = <&gcc GCC_PCIE_0_PHY_BCR>;

			reset-names = "lane0";

		};

		pciephy_1: lane@36000 {

		...

		...

	};

Qualcomm QUSB2 phy controller

=============================

QUSB2 controller supports LS/FS/HS usb connectivity on Qualcomm chipsets.

Required properties:

 - compatible: compatible list, contains "qcom,msm8996-qusb2-phy".

 - reg: offset and length of the PHY register set.

 - #phy-cells: must be 0.

 - clocks: a list of phandles and clock-specifier pairs,

	   one for each entry in clock-names.

 - clock-names: must be "cfg_ahb" for phy config clock,

			"ref" for 19.2 MHz ref clk,

			"iface" for phy interface clock (Optional).

 - vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll block.

 - vdda-phy-dpdm-supply: Phandle to 3.1V regulator supply to Dp/Dm port signals.

 - resets: Phandle to reset to phy block.

Optional properties:

 - nvmem-cells: Phandle to nvmem cell that contains 'HS Tx trim'

		tuning parameter value for qusb2 phy.

 - qcom,tcsr-syscon: Phandle to TCSR syscon register region.

Example:

	hsusb_phy: phy@7411000 {

		compatible = "qcom,msm8996-qusb2-phy";

		reg = <0x7411000 0x180>;

		#phy-cells = <0>;

		clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,

			<&gcc GCC_RX1_USB2_CLKREF_CLK>,

		clock-names = "cfg_ahb", "ref";

		vdda-pll-supply = <&pm8994_l12>;

		vdda-phy-dpdm-supply = <&pm8994_l24>;

		resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;

		nvmem-cells = <&qusb2p_hstx_trim>;

        };

- reset-names: Only allow the following entries:

- reset-names: Only allow the following entries:

 - phy-reset

 - phy-reset

- resets: Must contain an entry for each entry in reset-names.

- resets: Must contain an entry for each entry in reset-names.

- vbus-supply: power-supply phandle for vbus power source

Example:

Example: