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Commit a62d0834 authored by Imre Deak's avatar Imre Deak Committed by Daniel Vetter
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drm/i915: merge VLV eDP and DP AUX clock divider calculation 



On ValleyView for both eDP and DP the AUX input clock is 200MHz, so we
can calculate for both the clock divider for the 2MHz target rate at the
same place. Afterwards we can also replace the is_cpu_edp() check with a
check for port A.

Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 982a3866

drivers/gpu/drm/i915/intel_dp.c

+3 −3
Original line number Diff line number Diff line
@@ -317,12 +317,12 @@ intel_dp_aux_ch(struct intel_dp *intel_dp, 
	 * Note that PCH attached eDP panels should use a 125MHz input

	 * clock divider.

	 */

	if (is_cpu_edp(intel_dp)) {

	if (IS_VALLEYVIEW(dev)) {

		aux_clock_divider = 100;

	} else if (intel_dig_port->port == PORT_A) {

		if (HAS_DDI(dev))

			aux_clock_divider = DIV_ROUND_CLOSEST(

				intel_ddi_get_cdclk_freq(dev_priv), 2000);

		else if (IS_VALLEYVIEW(dev))

			aux_clock_divider = 100;

		else if (IS_GEN6(dev) || IS_GEN7(dev))

			aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */

		else