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Commit a4cd8f22 authored by Steve Longerbeam's avatar Steve Longerbeam Committed by Philipp Zabel
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gpu: ipu-v3: Move IDMAC channel names to imx-ipu-v3.h 



Move the IDMAC channel names to imx-ipu-v3.h, to make the names
available outside IPU. Add a couple new channels in the process
(async display BG/FG, channels 24 and 29).

Signed-off-by: default avatarSteve Longerbeam <steve_longerbeam@mentor.com>
Signed-off-by: default avatarPhilipp Zabel <p.zabel@pengutronix.de>
parent 4cea940d

drivers/gpu/ipu-v3/ipu-prv.h

+0 −25
Original line number Original line Diff line number Diff line
@@ -24,31 +24,6 @@ struct ipu_soc; 




#include <video/imx-ipu-v3.h>

#include <video/imx-ipu-v3.h>





#define IPUV3_CHANNEL_CSI0			 0

#define IPUV3_CHANNEL_CSI1			 1

#define IPUV3_CHANNEL_CSI2			 2

#define IPUV3_CHANNEL_CSI3			 3

#define IPUV3_CHANNEL_VDI_MEM_IC_VF              5

#define IPUV3_CHANNEL_MEM_IC_PP                 11

#define IPUV3_CHANNEL_MEM_IC_PRP_VF             12

#define IPUV3_CHANNEL_G_MEM_IC_PRP_VF           14

#define IPUV3_CHANNEL_G_MEM_IC_PP               15

#define IPUV3_CHANNEL_IC_PRP_ENC_MEM            20

#define IPUV3_CHANNEL_IC_PRP_VF_MEM             21

#define IPUV3_CHANNEL_IC_PP_MEM                 22

#define IPUV3_CHANNEL_MEM_BG_SYNC		23

#define IPUV3_CHANNEL_MEM_FG_SYNC		27

#define IPUV3_CHANNEL_MEM_DC_SYNC		28

#define IPUV3_CHANNEL_MEM_FG_SYNC_ALPHA		31

#define IPUV3_CHANNEL_MEM_DC_ASYNC		41

#define IPUV3_CHANNEL_MEM_ROT_ENC		45

#define IPUV3_CHANNEL_MEM_ROT_VF		46

#define IPUV3_CHANNEL_MEM_ROT_PP		47

#define IPUV3_CHANNEL_ROT_ENC_MEM		48

#define IPUV3_CHANNEL_ROT_VF_MEM		49

#define IPUV3_CHANNEL_ROT_PP_MEM		50

#define IPUV3_CHANNEL_MEM_BG_SYNC_ALPHA		51



#define IPU_MCU_T_DEFAULT	8

#define IPU_MCU_T_DEFAULT	8

#define IPU_CM_IDMAC_REG_OFS	0x00008000

#define IPU_CM_IDMAC_REG_OFS	0x00008000

#define IPU_CM_IC_REG_OFS	0x00020000

#define IPU_CM_IC_REG_OFS	0x00020000

include/video/imx-ipu-v3.h

+30 −0
Original line number Original line Diff line number Diff line
@@ -100,6 +100,36 @@ enum ipu_channel_irq { 
	IPU_IRQ_EOS = 192,

	IPU_IRQ_EOS = 192,

};

};





/*

 * Enumeration of IDMAC channels

 */

#define IPUV3_CHANNEL_CSI0			 0

#define IPUV3_CHANNEL_CSI1			 1

#define IPUV3_CHANNEL_CSI2			 2

#define IPUV3_CHANNEL_CSI3			 3

#define IPUV3_CHANNEL_VDI_MEM_IC_VF		 5

#define IPUV3_CHANNEL_MEM_IC_PP			11

#define IPUV3_CHANNEL_MEM_IC_PRP_VF		12

#define IPUV3_CHANNEL_G_MEM_IC_PRP_VF		14

#define IPUV3_CHANNEL_G_MEM_IC_PP		15

#define IPUV3_CHANNEL_IC_PRP_ENC_MEM		20

#define IPUV3_CHANNEL_IC_PRP_VF_MEM		21

#define IPUV3_CHANNEL_IC_PP_MEM			22

#define IPUV3_CHANNEL_MEM_BG_SYNC		23

#define IPUV3_CHANNEL_MEM_BG_ASYNC		24

#define IPUV3_CHANNEL_MEM_FG_SYNC		27

#define IPUV3_CHANNEL_MEM_DC_SYNC		28

#define IPUV3_CHANNEL_MEM_FG_ASYNC		29

#define IPUV3_CHANNEL_MEM_FG_SYNC_ALPHA		31

#define IPUV3_CHANNEL_MEM_DC_ASYNC		41

#define IPUV3_CHANNEL_MEM_ROT_ENC		45

#define IPUV3_CHANNEL_MEM_ROT_VF		46

#define IPUV3_CHANNEL_MEM_ROT_PP		47

#define IPUV3_CHANNEL_ROT_ENC_MEM		48

#define IPUV3_CHANNEL_ROT_VF_MEM		49

#define IPUV3_CHANNEL_ROT_PP_MEM		50

#define IPUV3_CHANNEL_MEM_BG_SYNC_ALPHA		51



int ipu_map_irq(struct ipu_soc *ipu, int irq);

int ipu_map_irq(struct ipu_soc *ipu, int irq);

int ipu_idmac_channel_irq(struct ipu_soc *ipu, struct ipuv3_channel *channel,

int ipu_idmac_channel_irq(struct ipu_soc *ipu, struct ipuv3_channel *channel,

		enum ipu_channel_irq irq);

		enum ipu_channel_irq irq);