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Unverified Commit a493ceae authored by Maxime Ripard's avatar Maxime Ripard
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drm/sun4i: tcon: Add TRI finish interrupt for vblank 



The "CPU" (or Intel 8080) interface uses a different interrupt called
TRI_FINISH (most likely TRI being for trigger) to notify the end of frames,
and hence the VBLANK period.

And that interrupt to the possible VBLANK interrupts source.

Reviewed-by: default avatarChen-Yu Tsai <wens@csie.org>
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@bootlin.com>
Link: https://patchwork.freedesktop.org/patch/msgid/de6d6ad8959da77ea3a974a31a4c0c8391178748.1522835818.git-series.maxime.ripard@bootlin.com
parent 1d0397d6

drivers/gpu/drm/sun4i/sun4i_tcon.c

+6 −3
Original line number Diff line number Diff line
@@ -201,7 +201,8 @@ void sun4i_tcon_enable_vblank(struct sun4i_tcon *tcon, bool enable) 
	DRM_DEBUG_DRIVER("%sabling VBLANK interrupt\n", enable ? "En" : "Dis");



	mask = SUN4I_TCON_GINT0_VBLANK_ENABLE(0) |

	       SUN4I_TCON_GINT0_VBLANK_ENABLE(1);

		SUN4I_TCON_GINT0_VBLANK_ENABLE(1) |

		SUN4I_TCON_GINT0_TCON0_TRI_FINISH_ENABLE;



	if (enable)

		val = mask;
@@ -582,7 +583,8 @@ static irqreturn_t sun4i_tcon_handler(int irq, void *private) 
	regmap_read(tcon->regs, SUN4I_TCON_GINT0_REG, &status);



	if (!(status & (SUN4I_TCON_GINT0_VBLANK_INT(0) |

			SUN4I_TCON_GINT0_VBLANK_INT(1))))

			SUN4I_TCON_GINT0_VBLANK_INT(1) |

			SUN4I_TCON_GINT0_TCON0_TRI_FINISH_INT)))

		return IRQ_NONE;



	drm_crtc_handle_vblank(&scrtc->crtc);
@@ -591,7 +593,8 @@ static irqreturn_t sun4i_tcon_handler(int irq, void *private) 
	/* Acknowledge the interrupt */

	regmap_update_bits(tcon->regs, SUN4I_TCON_GINT0_REG,

			   SUN4I_TCON_GINT0_VBLANK_INT(0) |

			   SUN4I_TCON_GINT0_VBLANK_INT(1),

			   SUN4I_TCON_GINT0_VBLANK_INT(1) |

			   SUN4I_TCON_GINT0_TCON0_TRI_FINISH_INT,

			   0);



	if (engine->ops->vblank_quirk)

drivers/gpu/drm/sun4i/sun4i_tcon.h

+4 −0
Original line number Diff line number Diff line
@@ -28,7 +28,11 @@ 


#define SUN4I_TCON_GINT0_REG			0x4

#define SUN4I_TCON_GINT0_VBLANK_ENABLE(pipe)		BIT(31 - (pipe))

#define SUN4I_TCON_GINT0_TCON0_TRI_FINISH_ENABLE	BIT(27)

#define SUN4I_TCON_GINT0_TCON0_TRI_COUNTER_ENABLE	BIT(26)

#define SUN4I_TCON_GINT0_VBLANK_INT(pipe)		BIT(15 - (pipe))

#define SUN4I_TCON_GINT0_TCON0_TRI_FINISH_INT		BIT(11)

#define SUN4I_TCON_GINT0_TCON0_TRI_COUNTER_INT		BIT(10)



#define SUN4I_TCON_GINT1_REG			0x8

#define SUN4I_TCON_FRM_CTL_REG			0x10