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Commit a41622ea authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge master.kernel.org:/home/rmk/linux-2.6-arm 

* master.kernel.org:/home/rmk/linux-2.6-arm:
  [ARM] 3030/2: fix permission check in the obscur cmpxchg syscall
  [ARM] nommu: rename compressed/head.S symbols to a new style
  [ARM] select TLS_REG_EMUL and NEEDS_SYSCALL_FOR_CMPXCHG
  [ARM] nommu: Move hardware page table definitions to pgtable-hwdef.h
  [ARM] Move read of processor ID out of lookup_processor_type()
  [ARM] Fix typo in tlbflush.h
  [ARM] noMMU: removes TLB codes in nommu mode
  [ARM] noMMU: block sys_fork in nommu mode
  [ARM] 3399/1: Fix link problem when CONFIG_PRINTK is disabled
  [ARM] 3398/1: Fix the VFP registers loading/storing base address
  [ARM] 3397/1: AT91RM9200 Header update
  [ARM] 3385/1: Battery support for sharp zaurus sl-5500 (collie)
  [ARM] SMP: don't set cpu_*_map in smp_prepare_boot_cpu
  include/linux/clk.h is betraying its ARM origins
  [ARM] Move enable_irq and disable_irq to assembler.h
  [ARM] 3391/1: use PLAT8250_DEV_PLATFORM{,1} for platform device id instead of 0/1
parents 0b5c59a1 2ce9804f

arch/arm/boot/compressed/head.S

+41 −41
Original line number Diff line number Diff line
@@ -358,7 +358,7 @@ __setup_mmu: sub r3, r4, #16384 @ Page directory size 
		str	r1, [r0]

		mov	pc, lr



__armv4_cache_on:

__armv4_mmu_cache_on:

		mov	r12, lr

		bl	__setup_mmu

		mov	r0, #0
@@ -367,24 +367,24 @@ __armv4_cache_on: 
		mrc	p15, 0, r0, c1, c0, 0	@ read control reg

		orr	r0, r0, #0x5000		@ I-cache enable, RR cache replacement

		orr	r0, r0, #0x0030

		bl	__common_cache_on

		bl	__common_mmu_cache_on

		mov	r0, #0

		mcr	p15, 0, r0, c8, c7, 0	@ flush I,D TLBs

		mov	pc, r12



__arm6_cache_on:

__arm6_mmu_cache_on:

		mov	r12, lr

		bl	__setup_mmu

		mov	r0, #0

		mcr	p15, 0, r0, c7, c0, 0	@ invalidate whole cache v3

		mcr	p15, 0, r0, c5, c0, 0	@ invalidate whole TLB v3

		mov	r0, #0x30

		bl	__common_cache_on

		bl	__common_mmu_cache_on

		mov	r0, #0

		mcr	p15, 0, r0, c5, c0, 0	@ invalidate whole TLB v3

		mov	pc, r12



__common_cache_on:

__common_mmu_cache_on:

#ifndef DEBUG

		orr	r0, r0, #0x000d		@ Write buffer, mmu

#endif
@@ -471,12 +471,12 @@ call_cache_fn: adr r12, proc_types 
proc_types:

		.word	0x41560600		@ ARM6/610

		.word	0xffffffe0

		b	__arm6_cache_off	@ works, but slow

		b	__arm6_cache_off

		b	__arm6_mmu_cache_off	@ works, but slow

		b	__arm6_mmu_cache_off

		mov	pc, lr

@		b	__arm6_cache_on		@ untested

@		b	__arm6_cache_off

@		b	__armv3_cache_flush

@		b	__arm6_mmu_cache_on		@ untested

@		b	__arm6_mmu_cache_off

@		b	__armv3_mmu_cache_flush



		.word	0x00000000		@ old ARM ID

		.word	0x0000f000
@@ -486,14 +486,14 @@ proc_types: 


		.word	0x41007000		@ ARM7/710

		.word	0xfff8fe00

		b	__arm7_cache_off

		b	__arm7_cache_off

		b	__arm7_mmu_cache_off

		b	__arm7_mmu_cache_off

		mov	pc, lr



		.word	0x41807200		@ ARM720T (writethrough)

		.word	0xffffff00

		b	__armv4_cache_on

		b	__armv4_cache_off

		b	__armv4_mmu_cache_on

		b	__armv4_mmu_cache_off

		mov	pc, lr



		.word	0x00007000		@ ARM7 IDs
@@ -506,41 +506,41 @@ proc_types: 


		.word	0x4401a100		@ sa110 / sa1100

		.word	0xffffffe0

		b	__armv4_cache_on

		b	__armv4_cache_off

		b	__armv4_cache_flush

		b	__armv4_mmu_cache_on

		b	__armv4_mmu_cache_off

		b	__armv4_mmu_cache_flush



		.word	0x6901b110		@ sa1110

		.word	0xfffffff0

		b	__armv4_cache_on

		b	__armv4_cache_off

		b	__armv4_cache_flush

		b	__armv4_mmu_cache_on

		b	__armv4_mmu_cache_off

		b	__armv4_mmu_cache_flush



		@ These match on the architecture ID



		.word	0x00020000		@ ARMv4T

		.word	0x000f0000

		b	__armv4_cache_on

		b	__armv4_cache_off

		b	__armv4_cache_flush

		b	__armv4_mmu_cache_on

		b	__armv4_mmu_cache_off

		b	__armv4_mmu_cache_flush



		.word	0x00050000		@ ARMv5TE

		.word	0x000f0000

		b	__armv4_cache_on

		b	__armv4_cache_off

		b	__armv4_cache_flush

		b	__armv4_mmu_cache_on

		b	__armv4_mmu_cache_off

		b	__armv4_mmu_cache_flush



		.word	0x00060000		@ ARMv5TEJ

		.word	0x000f0000

		b	__armv4_cache_on

		b	__armv4_cache_off

		b	__armv4_cache_flush

		b	__armv4_mmu_cache_on

		b	__armv4_mmu_cache_off

		b	__armv4_mmu_cache_flush



		.word	0x00070000		@ ARMv6

		.word	0x000f0000

		b	__armv4_cache_on

		b	__armv4_cache_off

		b	__armv6_cache_flush

		b	__armv4_mmu_cache_on

		b	__armv4_mmu_cache_off

		b	__armv6_mmu_cache_flush



		.word	0			@ unrecognised type

		.word	0
@@ -562,7 +562,7 @@ proc_types: 
cache_off:	mov	r3, #12			@ cache_off function

		b	call_cache_fn



__armv4_cache_off:

__armv4_mmu_cache_off:

		mrc	p15, 0, r0, c1, c0

		bic	r0, r0, #0x000d

		mcr	p15, 0, r0, c1, c0	@ turn MMU and cache off
@@ -571,15 +571,15 @@ __armv4_cache_off: 
		mcr	p15, 0, r0, c8, c7	@ invalidate whole TLB v4

		mov	pc, lr



__arm6_cache_off:

__arm6_mmu_cache_off:

		mov	r0, #0x00000030		@ ARM6 control reg.

		b	__armv3_cache_off

		b	__armv3_mmu_cache_off



__arm7_cache_off:

__arm7_mmu_cache_off:

		mov	r0, #0x00000070		@ ARM7 control reg.

		b	__armv3_cache_off

		b	__armv3_mmu_cache_off



__armv3_cache_off:

__armv3_mmu_cache_off:

		mcr	p15, 0, r0, c1, c0, 0	@ turn MMU and cache off

		mov	r0, #0

		mcr	p15, 0, r0, c7, c0, 0	@ invalidate whole cache v3
@@ -601,7 +601,7 @@ cache_clean_flush: 
		mov	r3, #16

		b	call_cache_fn



__armv6_cache_flush:

__armv6_mmu_cache_flush:

		mov	r1, #0

		mcr	p15, 0, r1, c7, c14, 0	@ clean+invalidate D

		mcr	p15, 0, r1, c7, c5, 0	@ invalidate I+BTB
@@ -609,7 +609,7 @@ __armv6_cache_flush: 
		mcr	p15, 0, r1, c7, c10, 4	@ drain WB

		mov	pc, lr



__armv4_cache_flush:

__armv4_mmu_cache_flush:

		mov	r2, #64*1024		@ default: 32K dcache size (*2)

		mov	r11, #32		@ default: 32 byte line size

		mrc	p15, 0, r3, c0, c0, 1	@ read cache type
@@ -637,7 +637,7 @@ no_cache_id: 
		mcr	p15, 0, r1, c7, c10, 4	@ drain WB

		mov	pc, lr



__armv3_cache_flush:

__armv3_mmu_cache_flush:

		mov	r1, #0

		mcr	p15, 0, r0, c7, c0, 0	@ invalidate whole cache v3

		mov	pc, lr

arch/arm/kernel/entry-header.S

+0 −18
Original line number Diff line number Diff line
@@ -37,24 +37,6 @@ 
#endif

	.endm



#if __LINUX_ARM_ARCH__ >= 6

	.macro	disable_irq

	cpsid	i

	.endm



	.macro	enable_irq

	cpsie	i

	.endm

#else

	.macro	disable_irq

	msr	cpsr_c, #PSR_I_BIT | SVC_MODE

	.endm



	.macro	enable_irq

	msr	cpsr_c, #SVC_MODE

	.endm

#endif



	.macro	get_thread_info, rd

	mov	\rd, sp, lsr #13

	mov	\rd, \rd, lsl #13

arch/arm/kernel/head.S

+9 −6
Original line number Diff line number Diff line
@@ -81,6 +81,7 @@ 
ENTRY(stext)

	msr	cpsr_c, #PSR_F_BIT | PSR_I_BIT | MODE_SVC @ ensure svc mode

						@ and irqs disabled

	mrc	p15, 0, r9, c0, c0		@ get processor id

	bl	__lookup_processor_type		@ r5=procinfo r9=cpuid

	movs	r10, r5				@ invalid processor (r5=0)?

	beq	__error_p			@ yes, error 'p'
@@ -155,6 +156,7 @@ ENTRY(secondary_startup) 
	 * as it has already been validated by the primary processor.

	 */

	msr	cpsr_c, #PSR_F_BIT | PSR_I_BIT | MODE_SVC

	mrc	p15, 0, r9, c0, c0		@ get processor id

	bl	__lookup_processor_type

	movs	r10, r5				@ invalid processor?

	moveq	r0, #'p'			@ yes, error 'p'
@@ -449,19 +451,19 @@ __error: 
 * (and therefore, we are not in the correct address space).  We have to

 * calculate the offset.

 *

 *	r9 = cpuid

 * Returns:

 *	r3, r4, r6 corrupted

 *	r5 = proc_info pointer in physical address space

 *	r9 = cpuid

 *	r9 = cpuid (preserved)

 */

	.type	__lookup_processor_type, %function

__lookup_processor_type:

	adr	r3, 3f

	ldmda	r3, {r5, r6, r9}

	sub	r3, r3, r9			@ get offset between virt&phys

	ldmda	r3, {r5 - r7}

	sub	r3, r3, r7			@ get offset between virt&phys

	add	r5, r5, r3			@ convert virt addresses to

	add	r6, r6, r3			@ physical address space

	mrc	p15, 0, r9, c0, c0		@ get processor id

1:	ldmia	r5, {r3, r4}			@ value, mask

	and	r4, r4, r9			@ mask wanted bits

	teq	r3, r4
@@ -476,10 +478,11 @@ __lookup_processor_type: 
 * This provides a C-API version of the above function.

 */

ENTRY(lookup_processor_type)

	stmfd	sp!, {r4 - r6, r9, lr}

	stmfd	sp!, {r4 - r7, r9, lr}

	mov	r9, r0

	bl	__lookup_processor_type

	mov	r0, r5

	ldmfd	sp!, {r4 - r6, r9, pc}

	ldmfd	sp!, {r4 - r7, r9, pc}



/*

 * Look in include/asm-arm/procinfo.h and arch/arm/kernel/arch.[ch] for

arch/arm/kernel/setup.c

+2 −2
Original line number Diff line number Diff line
@@ -278,7 +278,7 @@ int cpu_architecture(void) 
 * These functions re-use the assembly code in head.S, which

 * already provide the required functionality.

 */

extern struct proc_info_list *lookup_processor_type(void);

extern struct proc_info_list *lookup_processor_type(unsigned int);

extern struct machine_desc *lookup_machine_type(unsigned int);



static void __init setup_processor(void)
@@ -290,7 +290,7 @@ static void __init setup_processor(void) 
	 * types.  The linker builds this table for us from the

	 * entries in arch/arm/mm/proc-*.S

	 */

	list = lookup_processor_type();

	list = lookup_processor_type(processor_id);

	if (!list) {

		printk("CPU configuration botched (ID %08x), unable "

		       "to continue.\n", processor_id);

arch/arm/kernel/smp.c

+0 −3
Original line number Diff line number Diff line
@@ -337,9 +337,6 @@ void __init smp_prepare_boot_cpu(void) 
	unsigned int cpu = smp_processor_id();



	per_cpu(cpu_data, cpu).idle = current;



	cpu_set(cpu, cpu_present_map);

	cpu_set(cpu, cpu_online_map);

}



static void send_ipi_message(cpumask_t callmap, enum ipi_msg_type msg)