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Commit a3bbf0ac authored by Taniya Das's avatar Taniya Das Committed by Gerrit - the friendly Code Review server
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ARM: dts: msm: Add support for CPUFREQ HW for LITO 

Add cpufreq node with the corresponding domain registers and also update
the CPU nodes with the frequency domains.

Change-Id: Ia2b54eab30cc67c711256e067f2adb1d9bbc40fd
parent 40f346ef

qcom/lito.dtsi

+19 −0
Original line number Diff line number Diff line
@@ -44,6 +44,7 @@ 
			reg = <0x0 0x0>;

			enable-method = "psci";

			cache-size = <0x8000>;

			qcom,freq-domain = <&cpufreq_hw 0 6>;

			next-level-cache = <&L2_0>;

			L2_0: l2-cache {

			      compatible = "arm,arch-cache";
@@ -79,6 +80,7 @@ 
			reg = <0x0 0x100>;

			enable-method = "psci";

			cache-size = <0x8000>;

			qcom,freq-domain = <&cpufreq_hw 0 6>;

			next-level-cache = <&L2_100>;

			L2_100: l2-cache {

				compatible = "arm,arch-cache";
@@ -108,6 +110,7 @@ 
			reg = <0x0 0x200>;

			enable-method = "psci";

			cache-size = <0x8000>;

			qcom,freq-domain = <&cpufreq_hw 0 6>;

			next-level-cache = <&L2_200>;

			L2_200: l2-cache {

				compatible = "arm,arch-cache";
@@ -137,6 +140,7 @@ 
			reg = <0x0 0x300>;

			enable-method = "psci";

			cache-size = <0x8000>;

			qcom,freq-domain = <&cpufreq_hw 0 6>;

			next-level-cache = <&L2_300>;

			L2_300: l2-cache {

				compatible = "arm,arch-cache";
@@ -167,6 +171,7 @@ 
			reg = <0x0 0x400>;

			enable-method = "psci";

			cache-size = <0x8000>;

			qcom,freq-domain = <&cpufreq_hw 0 6>;

			next-level-cache = <&L2_400>;

			L2_400: l2-cache {

				compatible = "arm,arch-cache";
@@ -196,6 +201,7 @@ 
			reg = <0x0 0x500>;

			enable-method = "psci";

			cache-size = <0x8000>;

			qcom,freq-domain = <&cpufreq_hw 0 6>;

			next-level-cache = <&L2_500>;

			L2_500: l2-cache {

				compatible = "arm,arch-cache";
@@ -225,6 +231,7 @@ 
			reg = <0x0 0x600>;

			enable-method = "psci";

			cache-size = <0x10000>;

			qcom,freq-domain = <&cpufreq_hw 1 2>;

			next-level-cache = <&L2_600>;

			L2_600: l2-cache {

				compatible = "arm,arch-cache";
@@ -263,6 +270,7 @@ 
			reg = <0x0 0x700>;

			enable-method = "psci";

			cache-size = <0x10000>;

			qcom,freq-domain = <&cpufreq_hw 2 2>;

			next-level-cache = <&L2_700>;

			L2_700: l2-cache {

				compatible = "arm,arch-cache";
@@ -1120,6 +1128,17 @@ 
		#clock-cells = <1>;

	};



	cpufreq_hw: qcom,cpufreq-hw {

		compatible = "qcom,cpufreq-hw";

		reg = <0x18323000 0x1000>, <0x18325800 0x1000>,

			<0x18327800 0x1000>;

		reg-names = "freq-domain0", "freq-domain1",

			    "freq-domain2";

		clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;

		clock-names = "xo", "alternate";

		#freq-domain-cells = <2>;

	};



	spmi_bus: qcom,spmi@c440000 {

		compatible = "qcom,spmi-pmic-arb";

		reg = <0xc440000 0x1100>,