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Commit a3b86a6d authored by Linus Walleij's avatar Linus Walleij
Browse files

ARM: plat-nomadik: modernize MTU timer 



Modernize the MTU timer to rely on the clockevents core to
calculate mult and shift and setup the clock event.

Acked-by: default avatarAlessandro Rubini <rubini@unipv.it>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent d3e8b756

arch/arm/plat-nomadik/timer.c

+3 −20
Original line number Diff line number Diff line
@@ -20,12 +20,6 @@ 
#include <asm/mach/time.h>

#include <asm/sched_clock.h>



/*

 * Guaranteed runtime conversion range in seconds for

 * the clocksource and clockevent.

 */

#define MTU_MIN_RANGE 4



/*

 * The MTU device hosts four different counters, with 4 set of

 * registers. These are register names.
@@ -102,7 +96,6 @@ static int nmdk_clkevt_next(unsigned long evt, struct clock_event_device *ev) 
void nmdk_clkevt_reset(void)

{

	if (clkevt_periodic) {



		/* Timer: configure load and background-load, and fire it up */

		writel(nmdk_cycle, mtu_base + MTU_LR(1));

		writel(nmdk_cycle, mtu_base + MTU_BGLR(1));
@@ -120,7 +113,6 @@ void nmdk_clkevt_reset(void) 
static void nmdk_clkevt_mode(enum clock_event_mode mode,

			     struct clock_event_device *dev)

{



	switch (mode) {

	case CLOCK_EVT_MODE_PERIODIC:

		clkevt_periodic = true;
@@ -224,17 +216,8 @@ void __init nmdk_timer_init(void __iomem *base) 
	setup_sched_clock(nomadik_read_sched_clock, 32, rate);

#endif



	/* Timer 1 is used for events */



	clockevents_calc_mult_shift(&nmdk_clkevt, rate, MTU_MIN_RANGE);



	nmdk_clkevt.max_delta_ns =

		clockevent_delta2ns(0xffffffff, &nmdk_clkevt);

	nmdk_clkevt.min_delta_ns =

		clockevent_delta2ns(0x00000002, &nmdk_clkevt);

	nmdk_clkevt.cpumask	= cpumask_of(0);



	/* Register irq and clockevents */

	/* Timer 1 is used for events, register irq and clockevents */

	setup_irq(IRQ_MTU0, &nmdk_timer_irq);

	clockevents_register_device(&nmdk_clkevt);

	nmdk_clkevt.cpumask = cpumask_of(0);

	clockevents_config_and_register(&nmdk_clkevt, rate, 2, 0xffffffffU);

}