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Commit a3583202 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-fixes-for-v4.14-rc3' of git://people.freedesktop.org/~airlied/linux 

Pull drm fixes from Dave Airlie:
 "Regular fixes pull, some amdkfd, amdgpu, etnaviv, sun4i, qxl, tegra
  fixes.

  I've got an outstanding pull for i915 but it wasn't on an rc2 base so
  I wanted to ship these out first, I might get to it before rc3 or I
  might not"

* tag 'drm-fixes-for-v4.14-rc3' of git://people.freedesktop.org/~airlied/linux:
  drm/tegra: trace: Fix path to include
  qxl: fix framebuffer unpinning
  drm/sun4i: cec: Enable back CEC-pin framework
  drm/amdkfd: Print event limit messages only once per process
  drm/amdkfd: Fix kernel-queue wrapping bugs
  drm/amdkfd: Fix incorrect destroy_mqd parameter
  drm/radeon: disable hard reset in hibernate for APUs
  drm/amdgpu: revert tile table update for oland
  etnaviv: fix gem object list corruption
  etnaviv: fix submit error path
  qxl: fix primary surface handling
  drm/amdkfd: check for null dev to avoid a null pointer dereference
parents 35dbba31 2b702e72

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

+188 −1
Original line number Diff line number Diff line
@@ -636,7 +636,194 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev) 
				NUM_BANKS(ADDR_SURF_2_BANK);

		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)

			WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);

	} else if (adev->asic_type == CHIP_OLAND || adev->asic_type == CHIP_HAINAN) {

	} else if (adev->asic_type == CHIP_OLAND) {

		tilemode[0] =   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |

				ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

				PIPE_CONFIG(ADDR_SURF_P4_8x16) |

				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |

				NUM_BANKS(ADDR_SURF_16_BANK) |

				BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |

				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);

		tilemode[1] =   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |

				ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

				PIPE_CONFIG(ADDR_SURF_P4_8x16) |

				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |

				NUM_BANKS(ADDR_SURF_16_BANK) |

				BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |

				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);

		tilemode[2] =   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |

				ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

				PIPE_CONFIG(ADDR_SURF_P4_8x16) |

				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |

				NUM_BANKS(ADDR_SURF_16_BANK) |

				BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |

				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);

		tilemode[3] =   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |

				ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

				PIPE_CONFIG(ADDR_SURF_P4_8x16) |

				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |

				NUM_BANKS(ADDR_SURF_16_BANK) |

				BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |

				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);

		tilemode[4] =   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |

				ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

				PIPE_CONFIG(ADDR_SURF_P4_8x16) |

				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |

				NUM_BANKS(ADDR_SURF_16_BANK) |

				BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |

				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);

		tilemode[5] =   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |

				ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

				PIPE_CONFIG(ADDR_SURF_P4_8x16) |

				TILE_SPLIT(split_equal_to_row_size) |

				NUM_BANKS(ADDR_SURF_16_BANK) |

				BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |

				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);

		tilemode[6] =   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |

				ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

				PIPE_CONFIG(ADDR_SURF_P4_8x16) |

				TILE_SPLIT(split_equal_to_row_size) |

				NUM_BANKS(ADDR_SURF_16_BANK) |

				BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |

				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);

		tilemode[7] =   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |

				ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

				PIPE_CONFIG(ADDR_SURF_P4_8x16) |

				TILE_SPLIT(split_equal_to_row_size) |

				NUM_BANKS(ADDR_SURF_16_BANK) |

				BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |

				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);

		tilemode[8] =   MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |

				ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |

				PIPE_CONFIG(ADDR_SURF_P4_8x16) |

				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |

				NUM_BANKS(ADDR_SURF_16_BANK) |

				BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |

				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);

		tilemode[9] =   MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |

				ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

				PIPE_CONFIG(ADDR_SURF_P4_8x16) |

				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |

				NUM_BANKS(ADDR_SURF_16_BANK) |

				BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |

				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);

		tilemode[10] =  MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |

				ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

				PIPE_CONFIG(ADDR_SURF_P4_8x16) |

				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |

				NUM_BANKS(ADDR_SURF_16_BANK) |

				BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |

				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);

		tilemode[11] =  MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |

				ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

				PIPE_CONFIG(ADDR_SURF_P4_8x16) |

				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |

				NUM_BANKS(ADDR_SURF_16_BANK) |

				BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |

				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);

		tilemode[12] =  MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |

				ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

				PIPE_CONFIG(ADDR_SURF_P4_8x16) |

				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |

				NUM_BANKS(ADDR_SURF_16_BANK) |

				BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |

				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);

		tilemode[13] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |

				ARRAY_MODE(ARRAY_1D_TILED_THIN1) |

				PIPE_CONFIG(ADDR_SURF_P4_8x16) |

				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |

				NUM_BANKS(ADDR_SURF_16_BANK) |

				BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |

				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);

		tilemode[14] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |

				ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

				PIPE_CONFIG(ADDR_SURF_P4_8x16) |

				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |

				NUM_BANKS(ADDR_SURF_16_BANK) |

				BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |

				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);

		tilemode[15] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |

				ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

				PIPE_CONFIG(ADDR_SURF_P4_8x16) |

				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |

				NUM_BANKS(ADDR_SURF_16_BANK) |

				BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |

				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);

		tilemode[16] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |

				ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

				PIPE_CONFIG(ADDR_SURF_P4_8x16) |

				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |

				NUM_BANKS(ADDR_SURF_16_BANK) |

				BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |

				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);

		tilemode[17] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |

				ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

				PIPE_CONFIG(ADDR_SURF_P4_8x16) |

				TILE_SPLIT(split_equal_to_row_size) |

				NUM_BANKS(ADDR_SURF_16_BANK) |

				BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |

				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);

		tilemode[21] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |

				ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

				PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |

				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |

				NUM_BANKS(ADDR_SURF_16_BANK) |

				BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |

				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |

				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);

		tilemode[22] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |

				ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

				PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |

				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |

				NUM_BANKS(ADDR_SURF_16_BANK) |

				BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |

				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);

		tilemode[23] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |

				ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

				PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |

				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |

				NUM_BANKS(ADDR_SURF_16_BANK) |

				BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |

				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);

		tilemode[24] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |

				ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

				PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |

				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |

				NUM_BANKS(ADDR_SURF_16_BANK) |

				BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |

				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);

		tilemode[25] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |

				ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

				PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |

				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |

				NUM_BANKS(ADDR_SURF_8_BANK) |

				BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |

				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |

				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1);

		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)

			WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);

	} else if (adev->asic_type == CHIP_HAINAN) {

		tilemode[0] =   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |

				ARRAY_MODE(ARRAY_2D_TILED_THIN1) |

				PIPE_CONFIG(ADDR_SURF_P2) |

drivers/gpu/drm/amd/amdkfd/kfd_chardev.c

+2 −0
Original line number Diff line number Diff line
@@ -892,6 +892,8 @@ static int kfd_ioctl_get_tile_config(struct file *filep, 
	int err = 0;



	dev = kfd_device_by_id(args->gpu_id);

	if (!dev)

		return -EINVAL;



	dev->kfd2kgd->get_tile_config(dev->kgd, &config);

drivers/gpu/drm/amd/amdkfd/kfd_events.c

+4 −1
Original line number Diff line number Diff line
@@ -292,7 +292,10 @@ static int create_signal_event(struct file *devkfd, 
				struct kfd_event *ev)

{

	if (p->signal_event_count == KFD_SIGNAL_EVENT_LIMIT) {

		if (!p->signal_event_limit_reached) {

			pr_warn("Signal event wasn't created because limit was reached\n");

			p->signal_event_limit_reached = true;

		}

		return -ENOMEM;

	}

drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c

+16 −4
Original line number Diff line number Diff line
@@ -184,7 +184,7 @@ static void uninitialize(struct kernel_queue *kq) 
	if (kq->queue->properties.type == KFD_QUEUE_TYPE_HIQ)

		kq->mqd->destroy_mqd(kq->mqd,

					kq->queue->mqd,

					false,

					KFD_PREEMPT_TYPE_WAVEFRONT_RESET,

					QUEUE_PREEMPT_DEFAULT_TIMEOUT_MS,

					kq->queue->pipe,

					kq->queue->queue);
@@ -210,6 +210,11 @@ static int acquire_packet_buffer(struct kernel_queue *kq, 
	uint32_t wptr, rptr;

	unsigned int *queue_address;



	/* When rptr == wptr, the buffer is empty.

	 * When rptr == wptr + 1, the buffer is full.

	 * It is always rptr that advances to the position of wptr, rather than

	 * the opposite. So we can only use up to queue_size_dwords - 1 dwords.

	 */

	rptr = *kq->rptr_kernel;

	wptr = *kq->wptr_kernel;

	queue_address = (unsigned int *)kq->pq_kernel_addr;
@@ -219,11 +224,10 @@ static int acquire_packet_buffer(struct kernel_queue *kq, 
	pr_debug("wptr: %d\n", wptr);

	pr_debug("queue_address 0x%p\n", queue_address);



	available_size = (rptr - 1 - wptr + queue_size_dwords) %

	available_size = (rptr + queue_size_dwords - 1 - wptr) %

							queue_size_dwords;



	if (packet_size_in_dwords >= queue_size_dwords ||

			packet_size_in_dwords >= available_size) {

	if (packet_size_in_dwords > available_size) {

		/*

		 * make sure calling functions know

		 * acquire_packet_buffer() failed
@@ -233,6 +237,14 @@ static int acquire_packet_buffer(struct kernel_queue *kq, 
	}



	if (wptr + packet_size_in_dwords >= queue_size_dwords) {

		/* make sure after rolling back to position 0, there is

		 * still enough space.

		 */

		if (packet_size_in_dwords >= rptr) {

			*buffer_ptr = NULL;

			return -ENOMEM;

		}

		/* fill nops, roll back and start at position 0 */

		while (wptr > 0) {

			queue_address[wptr] = kq->nop_packet;

			wptr = (wptr + 1) % queue_size_dwords;

drivers/gpu/drm/amd/amdkfd/kfd_priv.h

+1 −0
Original line number Diff line number Diff line
@@ -521,6 +521,7 @@ struct kfd_process { 
	struct list_head signal_event_pages;

	u32 next_nonsignal_event_id;

	size_t signal_event_count;

	bool signal_event_limit_reached;

};



/**