fw-api: Incremental hw header file update for WCN7750 (a31c3d5c) · Commits · e / devices / android_kernel_fairphone_FP4

hw/wcn7750/v1/msmhwioreg.h

+4 −4

Original line number	Diff line number	Diff line
		@@ -19,7 +19,7 @@

		#include "msmhwiobase.h"

		#define SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE (HOST_SOC_WFSS_CE_REG_BASE + 0x00001000)
		#define HOST_SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE (HOST_SOC_WFSS_CE_REG_BASE + 0x00001000)
		#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR (HOST_SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x408)
		#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffff
		#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0
		@@ -27,7 +27,7 @@
		#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 8
		#define HWIO_WCSS_UMAC_WBM_R0_MISC_CONTROL_SPARE_CONTROL_BMSK 0xfffffffc
		#define HWIO_WCSS_UMAC_WBM_R0_MISC_CONTROL_SPARE_CONTROL_SHFT 2
		#define SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE (HOST_SOC_WFSS_CE_REG_BASE + 0x00000000)
		#define HOST_SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE (HOST_SOC_WFSS_CE_REG_BASE + 0x00000000)
		#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR (HOST_SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x0)
		#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xffffffff
		#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN \
		@@ -52,7 +52,7 @@
		out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN)
		#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00
		#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 8
		#define SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE (HOST_SOC_WFSS_CE_REG_BASE + 0x00003000)
		#define HOST_SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE (HOST_SOC_WFSS_CE_REG_BASE + 0x00003000)
		#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR (HOST_SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x0)
		#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff
		#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN \
		@@ -78,7 +78,7 @@
		#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00
		#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 8
		#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR (HOST_SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x400)
		#define SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE (HOST_SOC_WFSS_CE_REG_BASE + 0x00002000)
		#define HOST_SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE (HOST_SOC_WFSS_CE_REG_BASE + 0x00002000)
		#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR (HOST_SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x0)
		#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff
		#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN \

hw/wcn7750/v1/tx_msdu_extension.h

0 → 100644

+372 −0

File added.

Preview size limit exceeded, changes collapsed.

hw/wcn7750/v1/tx_rate_stats_info.h

0 → 100644

+106 −0

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		/*
		* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
		*
		* Permission to use, copy, modify, and/or distribute this software for any
		* purpose with or without fee is hereby granted, provided that the above
		* copyright notice and this permission notice appear in all copies.
		*
		* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
		* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
		* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
		* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
		* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
		* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
		* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
		*/


		#ifndef _TX_RATE_STATS_INFO_H_
		#define _TX_RATE_STATS_INFO_H_

		#define NUM_OF_DWORDS_TX_RATE_STATS_INFO 2

		struct tx_rate_stats_info {
		#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
		uint32_t tx_rate_stats_info_valid : 1,
		transmit_bw : 3,
		transmit_pkt_type : 4,
		transmit_stbc : 1,
		transmit_ldpc : 1,
		transmit_sgi : 2,
		transmit_mcs : 4,
		ofdma_transmission : 1,
		tones_in_ru : 12,
		transmit_nss : 3;
		uint32_t ppdu_transmission_tsf : 32;
		#else
		uint32_t transmit_nss : 3,
		tones_in_ru : 12,
		ofdma_transmission : 1,
		transmit_mcs : 4,
		transmit_sgi : 2,
		transmit_ldpc : 1,
		transmit_stbc : 1,
		transmit_pkt_type : 4,
		transmit_bw : 3,
		tx_rate_stats_info_valid : 1;
		uint32_t ppdu_transmission_tsf : 32;
		#endif
		};

		#define TX_RATE_STATS_INFO_TX_RATE_STATS_INFO_VALID_OFFSET 0x00000000
		#define TX_RATE_STATS_INFO_TX_RATE_STATS_INFO_VALID_LSB 0
		#define TX_RATE_STATS_INFO_TX_RATE_STATS_INFO_VALID_MSB 0
		#define TX_RATE_STATS_INFO_TX_RATE_STATS_INFO_VALID_MASK 0x00000001

		#define TX_RATE_STATS_INFO_TRANSMIT_BW_OFFSET 0x00000000
		#define TX_RATE_STATS_INFO_TRANSMIT_BW_LSB 1
		#define TX_RATE_STATS_INFO_TRANSMIT_BW_MSB 3
		#define TX_RATE_STATS_INFO_TRANSMIT_BW_MASK 0x0000000e

		#define TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_OFFSET 0x00000000
		#define TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_LSB 4
		#define TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_MSB 7
		#define TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_MASK 0x000000f0

		#define TX_RATE_STATS_INFO_TRANSMIT_STBC_OFFSET 0x00000000
		#define TX_RATE_STATS_INFO_TRANSMIT_STBC_LSB 8
		#define TX_RATE_STATS_INFO_TRANSMIT_STBC_MSB 8
		#define TX_RATE_STATS_INFO_TRANSMIT_STBC_MASK 0x00000100

		#define TX_RATE_STATS_INFO_TRANSMIT_LDPC_OFFSET 0x00000000
		#define TX_RATE_STATS_INFO_TRANSMIT_LDPC_LSB 9
		#define TX_RATE_STATS_INFO_TRANSMIT_LDPC_MSB 9
		#define TX_RATE_STATS_INFO_TRANSMIT_LDPC_MASK 0x00000200

		#define TX_RATE_STATS_INFO_TRANSMIT_SGI_OFFSET 0x00000000
		#define TX_RATE_STATS_INFO_TRANSMIT_SGI_LSB 10
		#define TX_RATE_STATS_INFO_TRANSMIT_SGI_MSB 11
		#define TX_RATE_STATS_INFO_TRANSMIT_SGI_MASK 0x00000c00

		#define TX_RATE_STATS_INFO_TRANSMIT_MCS_OFFSET 0x00000000
		#define TX_RATE_STATS_INFO_TRANSMIT_MCS_LSB 12
		#define TX_RATE_STATS_INFO_TRANSMIT_MCS_MSB 15
		#define TX_RATE_STATS_INFO_TRANSMIT_MCS_MASK 0x0000f000

		#define TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_OFFSET 0x00000000
		#define TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_LSB 16
		#define TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_MSB 16
		#define TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_MASK 0x00010000

		#define TX_RATE_STATS_INFO_TONES_IN_RU_OFFSET 0x00000000
		#define TX_RATE_STATS_INFO_TONES_IN_RU_LSB 17
		#define TX_RATE_STATS_INFO_TONES_IN_RU_MSB 28
		#define TX_RATE_STATS_INFO_TONES_IN_RU_MASK 0x1ffe0000

		#define TX_RATE_STATS_INFO_TRANSMIT_NSS_OFFSET 0x00000000
		#define TX_RATE_STATS_INFO_TRANSMIT_NSS_LSB 29
		#define TX_RATE_STATS_INFO_TRANSMIT_NSS_MSB 31
		#define TX_RATE_STATS_INFO_TRANSMIT_NSS_MASK 0xe0000000

		#define TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_OFFSET 0x00000004
		#define TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_LSB 0
		#define TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_MSB 31
		#define TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_MASK 0xffffffff

		#endif