Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit a296b162 authored by Rex Zhu's avatar Rex Zhu Committed by Alex Deucher
Browse files

drm/amd/display: Fix bug use wrong pp interface 



Used wrong pp interface, the original interface is
exposed by dpm on SI and paritial CI.

Pointed out by Francis David <david.francis@amd.com>

v2: dal only need to set min_dcefclk and min_fclk to smu.
    so use display_clock_voltage_request interface,
    instand of update all display configuration.

Acked-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarRex Zhu <Rex.Zhu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent eb7e5cfc

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

+10 −2
Original line number Diff line number Diff line
@@ -480,12 +480,20 @@ void pp_rv_set_display_requirement(struct pp_smu *pp, 
{

	struct dc_context *ctx = pp->ctx;

	struct amdgpu_device *adev = ctx->driver_context;

	void *pp_handle = adev->powerplay.pp_handle;

	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;

	struct pp_display_clock_request clock = {0};



	if (!pp_funcs || !pp_funcs->display_configuration_changed)

	if (!pp_funcs || !pp_funcs->display_clock_voltage_request)

		return;



	amdgpu_dpm_display_configuration_changed(adev);

	clock.clock_type = amd_pp_dcf_clock;

	clock.clock_freq_in_khz = req->hard_min_dcefclk_khz;

	pp_funcs->display_clock_voltage_request(pp_handle, &clock);



	clock.clock_type = amd_pp_f_clock;

	clock.clock_freq_in_khz = req->hard_min_fclk_khz;

	pp_funcs->display_clock_voltage_request(pp_handle, &clock);

}



void pp_rv_set_wm_ranges(struct pp_smu *pp,