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Commit a28bbd58 authored by Michel Dänzer's avatar Michel Dänzer Committed by Alex Deucher
Browse files

drm/radeon: Always disable RADEON_GEM_GTT_UC along with RADEON_GEM_GTT_WC 



Write-combining is a CPU feature. From the GPU POV, these both simply
mean no GPU<->CPU cache coherency.

Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarMichel Dänzer <michel.daenzer@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 96ea47c0

drivers/gpu/drm/radeon/radeon_object.c

+2 −2
Original line number Diff line number Diff line
@@ -231,7 +231,7 @@ int radeon_bo_create(struct radeon_device *rdev, 
	/* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit

	 * See https://bugs.freedesktop.org/show_bug.cgi?id=84627

	 */

	bo->flags &= ~RADEON_GEM_GTT_WC;

	bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC);

#elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT)

	/* Don't try to enable write-combining when it can't work, or things

	 * may be slow
@@ -243,7 +243,7 @@ int radeon_bo_create(struct radeon_device *rdev, 


	DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for "

		      "better performance thanks to write-combining\n");

	bo->flags &= ~RADEON_GEM_GTT_WC;

	bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC);

#endif



	radeon_ttm_placement_from_domain(bo, domain);