Loading msm/sde/sde_crtc.c +20 −12 Original line number Diff line number Diff line Loading @@ -4769,6 +4769,24 @@ int sde_crtc_vblank(struct drm_crtc *crtc, bool en) return 0; } static void sde_kms_add_ubwc_info(struct sde_kms_info *info, struct sde_mdss_cfg *catalog) { sde_kms_info_add_keyint(info, "UBWC version", catalog->ubwc_version); sde_kms_info_add_keyint(info, "UBWC macrotile_mode", catalog->macrotile_mode); sde_kms_info_add_keyint(info, "UBWC highest banking bit", catalog->mdp[0].highest_bank_bit); sde_kms_info_add_keyint(info, "UBWC swizzle", catalog->mdp[0].ubwc_swizzle); if (of_fdt_get_ddrtype() == LP_DDR4_TYPE) sde_kms_info_add_keystr(info, "DDR version", "DDR4"); else sde_kms_info_add_keystr(info, "DDR version", "DDR5"); } /** * sde_crtc_install_properties - install all drm properties for crtc * @crtc: Pointer to drm crtc structure Loading Loading @@ -4917,18 +4935,8 @@ static void sde_crtc_install_properties(struct drm_crtc *crtc, if (catalog->qseed_type == SDE_SSPP_SCALER_QSEED3LITE) sde_kms_info_add_keystr(info, "qseed_type", "qseed3lite"); sde_kms_info_add_keyint(info, "UBWC version", catalog->ubwc_version); sde_kms_info_add_keyint(info, "UBWC macrotile_mode", catalog->macrotile_mode); sde_kms_info_add_keyint(info, "UBWC highest banking bit", catalog->mdp[0].highest_bank_bit); sde_kms_info_add_keyint(info, "UBWC swizzle", catalog->mdp[0].ubwc_swizzle); if (of_fdt_get_ddrtype() == LP_DDR4_TYPE) sde_kms_info_add_keystr(info, "DDR version", "DDR4"); else sde_kms_info_add_keystr(info, "DDR version", "DDR5"); if (catalog->ubwc_version) sde_kms_add_ubwc_info(info, catalog); if (sde_is_custom_client()) { /* No support for SMART_DMA_V1 yet */ Loading msm/sde/sde_hw_catalog.c +4 −1 Original line number Diff line number Diff line Loading @@ -56,6 +56,9 @@ /* default ubwc version */ #define DEFAULT_SDE_UBWC_VERSION SDE_HW_UBWC_VER_10 /* No UBWC */ #define DEFAULT_SDE_UBWC_NONE 0x0 /* default ubwc static config register value */ #define DEFAULT_SDE_UBWC_STATIC 0x0 Loading Loading @@ -3195,7 +3198,7 @@ static int _sde_parse_prop_check(struct sde_mdss_cfg *cfg, cfg->ubwc_version = SDE_HW_UBWC_VER(PROP_VALUE_ACCESS(prop_value, UBWC_VERSION, 0)); if (!prop_exists[UBWC_VERSION]) cfg->ubwc_version = DEFAULT_SDE_UBWC_VERSION; cfg->ubwc_version = DEFAULT_SDE_UBWC_NONE; cfg->mdp[0].highest_bank_bit = PROP_VALUE_ACCESS(prop_value, BANK_BIT, 0); Loading Loading
msm/sde/sde_crtc.c +20 −12 Original line number Diff line number Diff line Loading @@ -4769,6 +4769,24 @@ int sde_crtc_vblank(struct drm_crtc *crtc, bool en) return 0; } static void sde_kms_add_ubwc_info(struct sde_kms_info *info, struct sde_mdss_cfg *catalog) { sde_kms_info_add_keyint(info, "UBWC version", catalog->ubwc_version); sde_kms_info_add_keyint(info, "UBWC macrotile_mode", catalog->macrotile_mode); sde_kms_info_add_keyint(info, "UBWC highest banking bit", catalog->mdp[0].highest_bank_bit); sde_kms_info_add_keyint(info, "UBWC swizzle", catalog->mdp[0].ubwc_swizzle); if (of_fdt_get_ddrtype() == LP_DDR4_TYPE) sde_kms_info_add_keystr(info, "DDR version", "DDR4"); else sde_kms_info_add_keystr(info, "DDR version", "DDR5"); } /** * sde_crtc_install_properties - install all drm properties for crtc * @crtc: Pointer to drm crtc structure Loading Loading @@ -4917,18 +4935,8 @@ static void sde_crtc_install_properties(struct drm_crtc *crtc, if (catalog->qseed_type == SDE_SSPP_SCALER_QSEED3LITE) sde_kms_info_add_keystr(info, "qseed_type", "qseed3lite"); sde_kms_info_add_keyint(info, "UBWC version", catalog->ubwc_version); sde_kms_info_add_keyint(info, "UBWC macrotile_mode", catalog->macrotile_mode); sde_kms_info_add_keyint(info, "UBWC highest banking bit", catalog->mdp[0].highest_bank_bit); sde_kms_info_add_keyint(info, "UBWC swizzle", catalog->mdp[0].ubwc_swizzle); if (of_fdt_get_ddrtype() == LP_DDR4_TYPE) sde_kms_info_add_keystr(info, "DDR version", "DDR4"); else sde_kms_info_add_keystr(info, "DDR version", "DDR5"); if (catalog->ubwc_version) sde_kms_add_ubwc_info(info, catalog); if (sde_is_custom_client()) { /* No support for SMART_DMA_V1 yet */ Loading
msm/sde/sde_hw_catalog.c +4 −1 Original line number Diff line number Diff line Loading @@ -56,6 +56,9 @@ /* default ubwc version */ #define DEFAULT_SDE_UBWC_VERSION SDE_HW_UBWC_VER_10 /* No UBWC */ #define DEFAULT_SDE_UBWC_NONE 0x0 /* default ubwc static config register value */ #define DEFAULT_SDE_UBWC_STATIC 0x0 Loading Loading @@ -3195,7 +3198,7 @@ static int _sde_parse_prop_check(struct sde_mdss_cfg *cfg, cfg->ubwc_version = SDE_HW_UBWC_VER(PROP_VALUE_ACCESS(prop_value, UBWC_VERSION, 0)); if (!prop_exists[UBWC_VERSION]) cfg->ubwc_version = DEFAULT_SDE_UBWC_VERSION; cfg->ubwc_version = DEFAULT_SDE_UBWC_NONE; cfg->mdp[0].highest_bank_bit = PROP_VALUE_ACCESS(prop_value, BANK_BIT, 0); Loading