Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit a280a46e authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
Browse files

Merge "ARM: dts: msm: Fix SDCC's interrupt setting"

parents 5cc5c770 d4afebe2
Loading
Loading
Loading
Loading
+2 −1
Original line number Diff line number Diff line
@@ -3205,7 +3205,8 @@
		reg = <0x8804000 0x1000>;
		reg-names = "hc_mem";

		interrupts = <0 204 0>, <0 222 0>;
		interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "hc_irq", "pwr_irq";

		qcom,bus-width = <4>;