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Commit a26ae754 authored by Rob Clark's avatar Rob Clark
Browse files

drm/msm: update generated headers 



Pull in a5xx registers.

Signed-off-by: default avatarRob Clark <robdclark@gmail.com>
parent 398efc46

drivers/gpu/drm/msm/adreno/a2xx.xml.h

+14 −13
Original line number Diff line number Diff line
@@ -8,16 +8,17 @@ This file was generated by the rules-ng-ng headergen tool in this git repository 
git clone https://github.com/freedreno/envytools.git



The rules-ng-ng source files this header was generated from are:

- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml               (    398 bytes, from 2015-09-24 17:25:31)

- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml               (    431 bytes, from 2016-04-26 17:56:44)

- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1572 bytes, from 2016-02-10 17:07:21)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32901 bytes, from 2015-05-20 20:03:14)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  11518 bytes, from 2016-02-10 21:03:25)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  16166 bytes, from 2016-02-11 21:20:31)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  83967 bytes, from 2016-02-10 17:07:21)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          ( 109916 bytes, from 2016-02-20 18:44:48)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32907 bytes, from 2016-11-26 23:01:08)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  12025 bytes, from 2016-11-26 23:01:08)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  22544 bytes, from 2016-11-26 23:01:08)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  83840 bytes, from 2016-11-26 23:01:08)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          ( 110765 bytes, from 2016-11-26 23:01:48)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml          (  90321 bytes, from 2016-11-28 16:50:05)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml         (   1773 bytes, from 2015-09-24 17:30:00)



Copyright (C) 2013-2015 by the following authors:

Copyright (C) 2013-2016 by the following authors:

- Rob Clark <robdclark@gmail.com> (robclark)

- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
@@ -206,12 +207,12 @@ enum a2xx_rb_copy_sample_select { 
};



enum a2xx_rb_blend_opcode {

	BLEND_DST_PLUS_SRC = 0,

	BLEND_SRC_MINUS_DST = 1,

	BLEND_MIN_DST_SRC = 2,

	BLEND_MAX_DST_SRC = 3,

	BLEND_DST_MINUS_SRC = 4,

	BLEND_DST_PLUS_SRC_BIAS = 5,

	BLEND2_DST_PLUS_SRC = 0,

	BLEND2_SRC_MINUS_DST = 1,

	BLEND2_MIN_DST_SRC = 2,

	BLEND2_MAX_DST_SRC = 3,

	BLEND2_DST_MINUS_SRC = 4,

	BLEND2_DST_PLUS_SRC_BIAS = 5,

};



enum adreno_mmu_clnt_beh {

drivers/gpu/drm/msm/adreno/a3xx.xml.h

+18 −20
Original line number Diff line number Diff line
@@ -8,13 +8,14 @@ This file was generated by the rules-ng-ng headergen tool in this git repository 
git clone https://github.com/freedreno/envytools.git



The rules-ng-ng source files this header was generated from are:

- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml               (    398 bytes, from 2015-09-24 17:25:31)

- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml               (    431 bytes, from 2016-04-26 17:56:44)

- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1572 bytes, from 2016-02-10 17:07:21)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32901 bytes, from 2015-05-20 20:03:14)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  11518 bytes, from 2016-02-10 21:03:25)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  16166 bytes, from 2016-02-11 21:20:31)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  83967 bytes, from 2016-02-10 17:07:21)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          ( 109916 bytes, from 2016-02-20 18:44:48)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32907 bytes, from 2016-11-26 23:01:08)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  12025 bytes, from 2016-11-26 23:01:08)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  22544 bytes, from 2016-11-26 23:01:08)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  83840 bytes, from 2016-11-26 23:01:08)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          ( 110765 bytes, from 2016-11-26 23:01:48)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml          (  90321 bytes, from 2016-11-28 16:50:05)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml         (   1773 bytes, from 2015-09-24 17:30:00)



Copyright (C) 2013-2016 by the following authors:
@@ -129,10 +130,14 @@ enum a3xx_tex_fmt { 
	TFMT_Z16_UNORM = 9,

	TFMT_X8Z24_UNORM = 10,

	TFMT_Z32_FLOAT = 11,

	TFMT_NV12_UV_TILED = 17,

	TFMT_NV12_Y_TILED = 19,

	TFMT_NV12_UV = 21,

	TFMT_NV12_Y = 23,

	TFMT_UV_64X32 = 16,

	TFMT_VU_64X32 = 17,

	TFMT_Y_64X32 = 18,

	TFMT_NV12_64X32 = 19,

	TFMT_UV_LINEAR = 20,

	TFMT_VU_LINEAR = 21,

	TFMT_Y_LINEAR = 22,

	TFMT_NV12_LINEAR = 23,

	TFMT_I420_Y = 24,

	TFMT_I420_U = 26,

	TFMT_I420_V = 27,
@@ -525,14 +530,6 @@ enum a3xx_uche_perfcounter_select { 
	UCHE_UCHEPERF_ACTIVE_CYCLES = 20,

};



enum a3xx_rb_blend_opcode {

	BLEND_DST_PLUS_SRC = 0,

	BLEND_SRC_MINUS_DST = 1,

	BLEND_DST_MINUS_SRC = 2,

	BLEND_MIN_DST_SRC = 3,

	BLEND_MAX_DST_SRC = 4,

};



enum a3xx_intp_mode {

	SMOOTH = 0,

	FLAT = 1,
@@ -1393,13 +1390,14 @@ static inline uint32_t A3XX_RB_COPY_CONTROL_MODE(enum adreno_rb_copy_control_mod 
{

	return ((val) << A3XX_RB_COPY_CONTROL_MODE__SHIFT) & A3XX_RB_COPY_CONTROL_MODE__MASK;

}

#define A3XX_RB_COPY_CONTROL_MSAA_SRGB_DOWNSAMPLE		0x00000080

#define A3XX_RB_COPY_CONTROL_FASTCLEAR__MASK			0x00000f00

#define A3XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT			8

static inline uint32_t A3XX_RB_COPY_CONTROL_FASTCLEAR(uint32_t val)

{

	return ((val) << A3XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT) & A3XX_RB_COPY_CONTROL_FASTCLEAR__MASK;

}

#define A3XX_RB_COPY_CONTROL_UNK12				0x00001000

#define A3XX_RB_COPY_CONTROL_DEPTH32_RESOLVE			0x00001000

#define A3XX_RB_COPY_CONTROL_GMEM_BASE__MASK			0xffffc000

#define A3XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT			14

static inline uint32_t A3XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val)
@@ -1472,7 +1470,7 @@ static inline uint32_t A3XX_RB_DEPTH_CONTROL_ZFUNC(enum adreno_compare_func val) 
{

	return ((val) << A3XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT) & A3XX_RB_DEPTH_CONTROL_ZFUNC__MASK;

}

#define A3XX_RB_DEPTH_CONTROL_BF_ENABLE				0x00000080

#define A3XX_RB_DEPTH_CONTROL_Z_CLAMP_ENABLE			0x00000080

#define A3XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE			0x80000000



#define REG_A3XX_RB_DEPTH_CLEAR					0x00002101

drivers/gpu/drm/msm/adreno/a4xx.xml.h

+80 −31
Original line number Diff line number Diff line
@@ -8,13 +8,14 @@ This file was generated by the rules-ng-ng headergen tool in this git repository 
git clone https://github.com/freedreno/envytools.git



The rules-ng-ng source files this header was generated from are:

- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml               (    398 bytes, from 2015-09-24 17:25:31)

- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml               (    431 bytes, from 2016-04-26 17:56:44)

- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1572 bytes, from 2016-02-10 17:07:21)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32901 bytes, from 2015-05-20 20:03:14)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  11518 bytes, from 2016-02-10 21:03:25)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  16166 bytes, from 2016-02-11 21:20:31)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  83967 bytes, from 2016-02-10 17:07:21)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          ( 109916 bytes, from 2016-02-20 18:44:48)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32907 bytes, from 2016-11-26 23:01:08)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  12025 bytes, from 2016-11-26 23:01:08)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  22544 bytes, from 2016-11-26 23:01:08)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  83840 bytes, from 2016-11-26 23:01:08)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          ( 110765 bytes, from 2016-11-26 23:01:48)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml          (  90321 bytes, from 2016-11-28 16:50:05)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml         (   1773 bytes, from 2015-09-24 17:30:00)



Copyright (C) 2013-2016 by the following authors:
@@ -46,6 +47,9 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 
enum a4xx_color_fmt {

	RB4_A8_UNORM = 1,

	RB4_R8_UNORM = 2,

	RB4_R8_SNORM = 3,

	RB4_R8_UINT = 4,

	RB4_R8_SINT = 5,

	RB4_R4G4B4A4_UNORM = 8,

	RB4_R5G5B5A1_UNORM = 10,

	RB4_R5G6B5_UNORM = 14,
@@ -89,17 +93,10 @@ enum a4xx_color_fmt { 


enum a4xx_tile_mode {

	TILE4_LINEAR = 0,

	TILE4_2 = 2,

	TILE4_3 = 3,

};



enum a4xx_rb_blend_opcode {

	BLEND_DST_PLUS_SRC = 0,

	BLEND_SRC_MINUS_DST = 1,

	BLEND_DST_MINUS_SRC = 2,

	BLEND_MIN_DST_SRC = 3,

	BLEND_MAX_DST_SRC = 4,

};



enum a4xx_vtx_fmt {

	VFMT4_32_FLOAT = 1,

	VFMT4_32_32_FLOAT = 2,
@@ -940,6 +937,7 @@ static inline uint32_t A4XX_RB_MODE_CONTROL_HEIGHT(uint32_t val) 
{

	return ((val >> 5) << A4XX_RB_MODE_CONTROL_HEIGHT__SHIFT) & A4XX_RB_MODE_CONTROL_HEIGHT__MASK;

}

#define A4XX_RB_MODE_CONTROL_ENABLE_GMEM			0x00010000



#define REG_A4XX_RB_RENDER_CONTROL				0x000020a1

#define A4XX_RB_RENDER_CONTROL_BINNING_PASS			0x00000001
@@ -1043,7 +1041,7 @@ static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_b 
}

#define A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK	0x000000e0

#define A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT	5

static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a4xx_rb_blend_opcode val)

static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)

{

	return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK;

}
@@ -1061,7 +1059,7 @@ static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb 
}

#define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK	0x00e00000

#define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT	21

static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a4xx_rb_blend_opcode val)

static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)

{

	return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK;

}
@@ -1073,12 +1071,18 @@ static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_r 
}



#define REG_A4XX_RB_BLEND_RED					0x000020f0

#define A4XX_RB_BLEND_RED_UINT__MASK				0x0000ffff

#define A4XX_RB_BLEND_RED_UINT__MASK				0x000000ff

#define A4XX_RB_BLEND_RED_UINT__SHIFT				0

static inline uint32_t A4XX_RB_BLEND_RED_UINT(uint32_t val)

{

	return ((val) << A4XX_RB_BLEND_RED_UINT__SHIFT) & A4XX_RB_BLEND_RED_UINT__MASK;

}

#define A4XX_RB_BLEND_RED_SINT__MASK				0x0000ff00

#define A4XX_RB_BLEND_RED_SINT__SHIFT				8

static inline uint32_t A4XX_RB_BLEND_RED_SINT(uint32_t val)

{

	return ((val) << A4XX_RB_BLEND_RED_SINT__SHIFT) & A4XX_RB_BLEND_RED_SINT__MASK;

}

#define A4XX_RB_BLEND_RED_FLOAT__MASK				0xffff0000

#define A4XX_RB_BLEND_RED_FLOAT__SHIFT				16

static inline uint32_t A4XX_RB_BLEND_RED_FLOAT(float val)
@@ -1095,12 +1099,18 @@ static inline uint32_t A4XX_RB_BLEND_RED_F32(float val) 
}



#define REG_A4XX_RB_BLEND_GREEN					0x000020f2

#define A4XX_RB_BLEND_GREEN_UINT__MASK				0x0000ffff

#define A4XX_RB_BLEND_GREEN_UINT__MASK				0x000000ff

#define A4XX_RB_BLEND_GREEN_UINT__SHIFT				0

static inline uint32_t A4XX_RB_BLEND_GREEN_UINT(uint32_t val)

{

	return ((val) << A4XX_RB_BLEND_GREEN_UINT__SHIFT) & A4XX_RB_BLEND_GREEN_UINT__MASK;

}

#define A4XX_RB_BLEND_GREEN_SINT__MASK				0x0000ff00

#define A4XX_RB_BLEND_GREEN_SINT__SHIFT				8

static inline uint32_t A4XX_RB_BLEND_GREEN_SINT(uint32_t val)

{

	return ((val) << A4XX_RB_BLEND_GREEN_SINT__SHIFT) & A4XX_RB_BLEND_GREEN_SINT__MASK;

}

#define A4XX_RB_BLEND_GREEN_FLOAT__MASK				0xffff0000

#define A4XX_RB_BLEND_GREEN_FLOAT__SHIFT			16

static inline uint32_t A4XX_RB_BLEND_GREEN_FLOAT(float val)
@@ -1117,12 +1127,18 @@ static inline uint32_t A4XX_RB_BLEND_GREEN_F32(float val) 
}



#define REG_A4XX_RB_BLEND_BLUE					0x000020f4

#define A4XX_RB_BLEND_BLUE_UINT__MASK				0x0000ffff

#define A4XX_RB_BLEND_BLUE_UINT__MASK				0x000000ff

#define A4XX_RB_BLEND_BLUE_UINT__SHIFT				0

static inline uint32_t A4XX_RB_BLEND_BLUE_UINT(uint32_t val)

{

	return ((val) << A4XX_RB_BLEND_BLUE_UINT__SHIFT) & A4XX_RB_BLEND_BLUE_UINT__MASK;

}

#define A4XX_RB_BLEND_BLUE_SINT__MASK				0x0000ff00

#define A4XX_RB_BLEND_BLUE_SINT__SHIFT				8

static inline uint32_t A4XX_RB_BLEND_BLUE_SINT(uint32_t val)

{

	return ((val) << A4XX_RB_BLEND_BLUE_SINT__SHIFT) & A4XX_RB_BLEND_BLUE_SINT__MASK;

}

#define A4XX_RB_BLEND_BLUE_FLOAT__MASK				0xffff0000

#define A4XX_RB_BLEND_BLUE_FLOAT__SHIFT				16

static inline uint32_t A4XX_RB_BLEND_BLUE_FLOAT(float val)
@@ -1139,12 +1155,18 @@ static inline uint32_t A4XX_RB_BLEND_BLUE_F32(float val) 
}



#define REG_A4XX_RB_BLEND_ALPHA					0x000020f6

#define A4XX_RB_BLEND_ALPHA_UINT__MASK				0x0000ffff

#define A4XX_RB_BLEND_ALPHA_UINT__MASK				0x000000ff

#define A4XX_RB_BLEND_ALPHA_UINT__SHIFT				0

static inline uint32_t A4XX_RB_BLEND_ALPHA_UINT(uint32_t val)

{

	return ((val) << A4XX_RB_BLEND_ALPHA_UINT__SHIFT) & A4XX_RB_BLEND_ALPHA_UINT__MASK;

}

#define A4XX_RB_BLEND_ALPHA_SINT__MASK				0x0000ff00

#define A4XX_RB_BLEND_ALPHA_SINT__SHIFT				8

static inline uint32_t A4XX_RB_BLEND_ALPHA_SINT(uint32_t val)

{

	return ((val) << A4XX_RB_BLEND_ALPHA_SINT__SHIFT) & A4XX_RB_BLEND_ALPHA_SINT__MASK;

}

#define A4XX_RB_BLEND_ALPHA_FLOAT__MASK				0xffff0000

#define A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT			16

static inline uint32_t A4XX_RB_BLEND_ALPHA_FLOAT(float val)
@@ -1348,7 +1370,7 @@ static inline uint32_t A4XX_RB_DEPTH_CONTROL_ZFUNC(enum adreno_compare_func val) 
{

	return ((val) << A4XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT) & A4XX_RB_DEPTH_CONTROL_ZFUNC__MASK;

}

#define A4XX_RB_DEPTH_CONTROL_BF_ENABLE				0x00000080

#define A4XX_RB_DEPTH_CONTROL_Z_CLAMP_ENABLE			0x00000080

#define A4XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE			0x00010000

#define A4XX_RB_DEPTH_CONTROL_FORCE_FRAGZ_TO_FS			0x00020000

#define A4XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE			0x80000000
@@ -2177,11 +2199,23 @@ static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1_REG(uint32_t i0) 


#define REG_A4XX_CP_DRAW_STATE_ADDR				0x00000232



#define REG_A4XX_CP_PROTECT_REG_0				0x00000240



static inline uint32_t REG_A4XX_CP_PROTECT(uint32_t i0) { return 0x00000240 + 0x1*i0; }



static inline uint32_t REG_A4XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000240 + 0x1*i0; }

#define A4XX_CP_PROTECT_REG_BASE_ADDR__MASK			0x0001ffff

#define A4XX_CP_PROTECT_REG_BASE_ADDR__SHIFT			0

static inline uint32_t A4XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val)

{

	return ((val) << A4XX_CP_PROTECT_REG_BASE_ADDR__SHIFT) & A4XX_CP_PROTECT_REG_BASE_ADDR__MASK;

}

#define A4XX_CP_PROTECT_REG_MASK_LEN__MASK			0x1f000000

#define A4XX_CP_PROTECT_REG_MASK_LEN__SHIFT			24

static inline uint32_t A4XX_CP_PROTECT_REG_MASK_LEN(uint32_t val)

{

	return ((val) << A4XX_CP_PROTECT_REG_MASK_LEN__SHIFT) & A4XX_CP_PROTECT_REG_MASK_LEN__MASK;

}

#define A4XX_CP_PROTECT_REG_TRAP_WRITE				0x20000000

#define A4XX_CP_PROTECT_REG_TRAP_READ				0x40000000



#define REG_A4XX_CP_PROTECT_CTRL				0x00000250
@@ -2272,7 +2306,7 @@ static inline uint32_t A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 
{

	return ((val) << A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK;

}

#define A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK		0x0003fc00

#define A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK		0x0000fc00

#define A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT		10

static inline uint32_t A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)

{
@@ -2420,7 +2454,7 @@ static inline uint32_t A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 
{

	return ((val) << A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK;

}

#define A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK		0x0003fc00

#define A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK		0x0000fc00

#define A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT		10

static inline uint32_t A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)

{
@@ -3117,6 +3151,8 @@ static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_GS(uint32_t val) 


#define REG_A4XX_GRAS_CL_CLIP_CNTL				0x00002000

#define A4XX_GRAS_CL_CLIP_CNTL_CLIP_DISABLE			0x00008000

#define A4XX_GRAS_CL_CLIP_CNTL_ZNEAR_CLIP_DISABLE		0x00010000

#define A4XX_GRAS_CL_CLIP_CNTL_ZFAR_CLIP_DISABLE		0x00020000

#define A4XX_GRAS_CL_CLIP_CNTL_ZERO_GB_SCALE_Z			0x00400000



#define REG_A4XX_GRAS_CLEAR_CNTL				0x00002003
@@ -3253,6 +3289,7 @@ static inline uint32_t A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(float val) 
	return ((((int32_t)(val * 4.0))) << A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT) & A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK;

}

#define A4XX_GRAS_SU_MODE_CONTROL_POLY_OFFSET			0x00000800

#define A4XX_GRAS_SU_MODE_CONTROL_MSAA_ENABLE			0x00002000

#define A4XX_GRAS_SU_MODE_CONTROL_RENDERING_PASS		0x00100000



#define REG_A4XX_GRAS_SC_CONTROL				0x0000207b
@@ -3670,6 +3707,8 @@ static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH(uint32_t val) 
#define REG_A4XX_PC_BINNING_COMMAND				0x00000d00

#define A4XX_PC_BINNING_COMMAND_BINNING_ENABLE			0x00000001



#define REG_A4XX_PC_TESSFACTOR_ADDR				0x00000d08



#define REG_A4XX_PC_DRAWCALL_SETUP_OVERRIDE			0x00000d0c



#define REG_A4XX_PC_PERFCTR_PC_SEL_0				0x00000d10
@@ -3690,6 +3729,20 @@ static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH(uint32_t val) 


#define REG_A4XX_PC_BIN_BASE					0x000021c0



#define REG_A4XX_PC_VSTREAM_CONTROL				0x000021c2

#define A4XX_PC_VSTREAM_CONTROL_SIZE__MASK			0x003f0000

#define A4XX_PC_VSTREAM_CONTROL_SIZE__SHIFT			16

static inline uint32_t A4XX_PC_VSTREAM_CONTROL_SIZE(uint32_t val)

{

	return ((val) << A4XX_PC_VSTREAM_CONTROL_SIZE__SHIFT) & A4XX_PC_VSTREAM_CONTROL_SIZE__MASK;

}

#define A4XX_PC_VSTREAM_CONTROL_N__MASK				0x07c00000

#define A4XX_PC_VSTREAM_CONTROL_N__SHIFT			22

static inline uint32_t A4XX_PC_VSTREAM_CONTROL_N(uint32_t val)

{

	return ((val) << A4XX_PC_VSTREAM_CONTROL_N__SHIFT) & A4XX_PC_VSTREAM_CONTROL_N__MASK;

}



#define REG_A4XX_PC_PRIM_VTX_CNTL				0x000021c4

#define A4XX_PC_PRIM_VTX_CNTL_VAROUT__MASK			0x0000000f

#define A4XX_PC_PRIM_VTX_CNTL_VAROUT__SHIFT			0
@@ -3752,12 +3805,8 @@ static inline uint32_t A4XX_PC_HS_PARAM_SPACING(enum a4xx_tess_spacing val) 
{

	return ((val) << A4XX_PC_HS_PARAM_SPACING__SHIFT) & A4XX_PC_HS_PARAM_SPACING__MASK;

}

#define A4XX_PC_HS_PARAM_PRIMTYPE__MASK				0x01800000

#define A4XX_PC_HS_PARAM_PRIMTYPE__SHIFT			23

static inline uint32_t A4XX_PC_HS_PARAM_PRIMTYPE(enum adreno_pa_su_sc_draw val)

{

	return ((val) << A4XX_PC_HS_PARAM_PRIMTYPE__SHIFT) & A4XX_PC_HS_PARAM_PRIMTYPE__MASK;

}

#define A4XX_PC_HS_PARAM_CW					0x00800000

#define A4XX_PC_HS_PARAM_CONNECTED				0x01000000



#define REG_A4XX_VBIF_VERSION					0x00003000

drivers/gpu/drm/msm/adreno/a5xx.xml.h

0 → 100644
+3757 −0

File added.

Preview size limit exceeded, changes collapsed.

drivers/gpu/drm/msm/adreno/adreno_common.xml.h

+15 −6
Original line number Diff line number Diff line
@@ -8,13 +8,14 @@ This file was generated by the rules-ng-ng headergen tool in this git repository 
git clone https://github.com/freedreno/envytools.git



The rules-ng-ng source files this header was generated from are:

- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml               (    398 bytes, from 2015-09-24 17:25:31)

- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml               (    431 bytes, from 2016-04-26 17:56:44)

- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1572 bytes, from 2016-02-10 17:07:21)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32901 bytes, from 2015-05-20 20:03:14)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  11518 bytes, from 2016-02-10 21:03:25)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  16166 bytes, from 2016-02-11 21:20:31)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  83967 bytes, from 2016-02-10 17:07:21)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          ( 109916 bytes, from 2016-02-20 18:44:48)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32907 bytes, from 2016-11-26 23:01:08)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  12025 bytes, from 2016-11-26 23:01:08)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  22544 bytes, from 2016-11-26 23:01:08)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  83840 bytes, from 2016-11-26 23:01:08)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          ( 110765 bytes, from 2016-11-26 23:01:48)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml          (  90321 bytes, from 2016-11-28 16:50:05)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml         (   1773 bytes, from 2015-09-24 17:30:00)



Copyright (C) 2013-2016 by the following authors:
@@ -172,6 +173,14 @@ enum a3xx_color_swap { 
	XYZW = 3,

};



enum a3xx_rb_blend_opcode {

	BLEND_DST_PLUS_SRC = 0,

	BLEND_SRC_MINUS_DST = 1,

	BLEND_DST_MINUS_SRC = 2,

	BLEND_MIN_DST_SRC = 3,

	BLEND_MAX_DST_SRC = 4,

};



#define REG_AXXX_CP_RB_BASE					0x000001c0



#define REG_AXXX_CP_RB_CNTL					0x000001c1