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Commit a1ca802d authored by Jani Nikula's avatar Jani Nikula Committed by Daniel Vetter
Browse files

drm/i915: drop redundant warnings on not holding dpio_lock 



The lower level sideband read/write functions already do this.

Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Reviewed-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 5a09ae9f

drivers/gpu/drm/i915/intel_dp.c

+0 −6
Original line number Diff line number Diff line
@@ -1442,8 +1442,6 @@ static void intel_pre_enable_dp(struct intel_encoder *encoder) 
		int pipe = intel_crtc->pipe;

		u32 val;



		WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));



		val = intel_dpio_read(dev_priv, DPIO_DATA_LANE_A(port));

		val = 0;

		if (pipe)
@@ -1470,8 +1468,6 @@ static void intel_dp_pre_pll_enable(struct intel_encoder *encoder) 
	if (!IS_VALLEYVIEW(dev))

		return;



	WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));



	/* Program Tx lane resets to default */

	intel_dpio_write(dev_priv, DPIO_PCS_TX(port),

			 DPIO_PCS_TX_LANE2_RESET |
@@ -1622,8 +1618,6 @@ static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp) 
	uint8_t train_set = intel_dp->train_set[0];

	int port = vlv_dport_to_channel(dport);



	WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));



	switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {

	case DP_TRAIN_PRE_EMPHASIS_0:

		preemph_reg_value = 0x0004000;

drivers/gpu/drm/i915/intel_hdmi.c

+0 −4
Original line number Diff line number Diff line
@@ -1018,8 +1018,6 @@ static void intel_hdmi_pre_enable(struct intel_encoder *encoder) 
	if (!IS_VALLEYVIEW(dev))

		return;



	WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));



	/* Enable clock channels for this port */

	val = intel_dpio_read(dev_priv, DPIO_DATA_LANE_A(port));

	val = 0;
@@ -1063,8 +1061,6 @@ static void intel_hdmi_pre_pll_enable(struct intel_encoder *encoder) 
	if (!IS_VALLEYVIEW(dev))

		return;



	WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));



	/* Program Tx lane resets to default */

	intel_dpio_write(dev_priv, DPIO_PCS_TX(port),

			 DPIO_PCS_TX_LANE2_RESET |