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Commit a18d0699 authored by Alexandre Belloni's avatar Alexandre Belloni Committed by Nicolas Ferre
Browse files

ARM: at91/pm: move the standby functions to pm.c 



The standby functions are now only used in pm.c, move them there.

Also, they are not inlined as a pointer to those functions is passed to the
cpuidle driver.

Signed-off-by: default avatarAlexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: default avatarNicolas Ferre <nicolas.ferre@atmel.com>
parent 176a1b3d

arch/arm/mach-at91/pm.c

+89 −0
Original line number Diff line number Diff line
@@ -216,6 +216,95 @@ static void at91_pm_set_standby(void (*at91_standby)(void)) 
		at91_cpuidle_device.dev.platform_data = at91_standby;

}



/*

 * The AT91RM9200 goes into self-refresh mode with this command, and will

 * terminate self-refresh automatically on the next SDRAM access.

 *

 * Self-refresh mode is exited as soon as a memory access is made, but we don't

 * know for sure when that happens. However, we need to restore the low-power

 * mode if it was enabled before going idle. Restoring low-power mode while

 * still in self-refresh is "not recommended", but seems to work.

 */

static void at91rm9200_standby(void)

{

	u32 lpr = at91_ramc_read(0, AT91RM9200_SDRAMC_LPR);



	asm volatile(

		"b    1f\n\t"

		".align    5\n\t"

		"1:  mcr    p15, 0, %0, c7, c10, 4\n\t"

		"    str    %0, [%1, %2]\n\t"

		"    str    %3, [%1, %4]\n\t"

		"    mcr    p15, 0, %0, c7, c0, 4\n\t"

		"    str    %5, [%1, %2]"

		:

		: "r" (0), "r" (at91_ramc_base[0]), "r" (AT91RM9200_SDRAMC_LPR),

		  "r" (1), "r" (AT91RM9200_SDRAMC_SRR),

		  "r" (lpr));

}



/* We manage both DDRAM/SDRAM controllers, we need more than one value to

 * remember.

 */

static void at91_ddr_standby(void)

{

	/* Those two values allow us to delay self-refresh activation

	 * to the maximum. */

	u32 lpr0, lpr1 = 0;

	u32 saved_lpr0, saved_lpr1 = 0;



	if (at91_ramc_base[1]) {

		saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);

		lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;

		lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;

	}



	saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);

	lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;

	lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;



	/* self-refresh mode now */

	at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);

	if (at91_ramc_base[1])

		at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);



	cpu_do_idle();



	at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);

	if (at91_ramc_base[1])

		at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);

}



/* We manage both DDRAM/SDRAM controllers, we need more than one value to

 * remember.

 */

static void at91sam9_sdram_standby(void)

{

	u32 lpr0, lpr1 = 0;

	u32 saved_lpr0, saved_lpr1 = 0;



	if (at91_ramc_base[1]) {

		saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR);

		lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB;

		lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH;

	}



	saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR);

	lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB;

	lpr0 |= AT91_SDRAMC_LPCB_SELF_REFRESH;



	/* self-refresh mode now */

	at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0);

	if (at91_ramc_base[1])

		at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1);



	cpu_do_idle();



	at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0);

	if (at91_ramc_base[1])

		at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1);

}



static const struct of_device_id ramc_ids[] __initconst = {

	{ .compatible = "atmel,at91rm9200-sdramc", .data = at91rm9200_standby },

	{ .compatible = "atmel,at91sam9260-sdramc", .data = at91sam9_sdram_standby },

arch/arm/mach-at91/pm.h

+0 −92
Original line number Diff line number Diff line
@@ -23,96 +23,4 @@ 


#define	AT91_PM_SLOW_CLOCK	0x01



/*

 * The AT91RM9200 goes into self-refresh mode with this command, and will

 * terminate self-refresh automatically on the next SDRAM access.

 *

 * Self-refresh mode is exited as soon as a memory access is made, but we don't

 * know for sure when that happens. However, we need to restore the low-power

 * mode if it was enabled before going idle. Restoring low-power mode while

 * still in self-refresh is "not recommended", but seems to work.

 */



#ifndef __ASSEMBLY__

static inline void at91rm9200_standby(void)

{

	u32 lpr = at91_ramc_read(0, AT91RM9200_SDRAMC_LPR);



	asm volatile(

		"b    1f\n\t"

		".align    5\n\t"

		"1:  mcr    p15, 0, %0, c7, c10, 4\n\t"

		"    str    %0, [%1, %2]\n\t"

		"    str    %3, [%1, %4]\n\t"

		"    mcr    p15, 0, %0, c7, c0, 4\n\t"

		"    str    %5, [%1, %2]"

		:

		: "r" (0), "r" (at91_ramc_base[0]), "r" (AT91RM9200_SDRAMC_LPR),

		  "r" (1), "r" (AT91RM9200_SDRAMC_SRR),

		  "r" (lpr));

}



/* We manage both DDRAM/SDRAM controllers, we need more than one value to

 * remember.

 */

static inline void at91_ddr_standby(void)

{

	/* Those two values allow us to delay self-refresh activation

	 * to the maximum. */

	u32 lpr0, lpr1 = 0;

	u32 saved_lpr0, saved_lpr1 = 0;



	if (at91_ramc_base[1]) {

		saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);

		lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;

		lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;

	}



	saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);

	lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;

	lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;



	/* self-refresh mode now */

	at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);

	if (at91_ramc_base[1])

		at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);



	cpu_do_idle();



	at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);

	if (at91_ramc_base[1])

		at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);

}



/* We manage both DDRAM/SDRAM controllers, we need more than one value to

 * remember.

 */

static inline void at91sam9_sdram_standby(void)

{

	u32 lpr0, lpr1 = 0;

	u32 saved_lpr0, saved_lpr1 = 0;



	if (at91_ramc_base[1]) {

		saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR);

		lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB;

		lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH;

	}



	saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR);

	lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB;

	lpr0 |= AT91_SDRAMC_LPCB_SELF_REFRESH;



	/* self-refresh mode now */

	at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0);

	if (at91_ramc_base[1])

		at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1);



	cpu_do_idle();



	at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0);

	if (at91_ramc_base[1])

		at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1);

}



#endif

#endif