Loading arch/arm/boot/dts/imx51-babbage.dts +27 −1 Original line number Diff line number Diff line Loading @@ -162,6 +162,11 @@ }; }; }; ssi2: ssi@70014000 { fsl,mode = "i2s-slave"; status = "okay"; }; }; wdog@73f98000 { /* WDOG1 */ Loading Loading @@ -191,10 +196,17 @@ i2c@83fc4000 { /* I2C2 */ status = "okay"; codec: sgtl5000@0a { sgtl5000: codec@0a { compatible = "fsl,sgtl5000"; reg = <0x0a>; clock-frequency = <26000000>; VDDA-supply = <&vdig_reg>; VDDIO-supply = <&vvideo_reg>; }; }; audmux@83fd0000 { status = "okay"; }; ethernet@83fec000 { Loading @@ -214,4 +226,18 @@ gpio-key,wakeup; }; }; sound { compatible = "fsl,imx51-babbage-sgtl5000", "fsl,imx-audio-sgtl5000"; model = "imx51-babbage-sgtl5000"; ssi-controller = <&ssi2>; audio-codec = <&sgtl5000>; audio-routing = "MIC_IN", "Mic Jack", "Mic Jack", "Mic Bias", "Headphone Jack", "HP_OUT"; mux-int-port = <2>; mux-ext-port = <3>; }; }; arch/arm/boot/dts/imx51.dtsi +33 −0 Original line number Diff line number Diff line Loading @@ -102,6 +102,15 @@ status = "disabled"; }; ssi2: ssi@70014000 { compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; reg = <0x70014000 0x4000>; interrupts = <30>; fsl,fifo-depth = <15>; fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */ status = "disabled"; }; esdhc@70020000 { /* ESDHC3 */ compatible = "fsl,imx51-esdhc"; reg = <0x70020000 0x4000>; Loading Loading @@ -235,6 +244,30 @@ status = "disabled"; }; ssi1: ssi@83fcc000 { compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; reg = <0x83fcc000 0x4000>; interrupts = <29>; fsl,fifo-depth = <15>; fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */ status = "disabled"; }; audmux@83fd0000 { compatible = "fsl,imx51-audmux", "fsl,imx31-audmux"; reg = <0x83fd0000 0x4000>; status = "disabled"; }; ssi3: ssi@83fe8000 { compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; reg = <0x83fe8000 0x4000>; interrupts = <96>; fsl,fifo-depth = <15>; fsl,ssi-dma-events = <47 46 37 35>; /* TX0 RX0 TX1 RX1 */ status = "disabled"; }; ethernet@83fec000 { compatible = "fsl,imx51-fec", "fsl,imx27-fec"; reg = <0x83fec000 0x4000>; Loading Loading
arch/arm/boot/dts/imx51-babbage.dts +27 −1 Original line number Diff line number Diff line Loading @@ -162,6 +162,11 @@ }; }; }; ssi2: ssi@70014000 { fsl,mode = "i2s-slave"; status = "okay"; }; }; wdog@73f98000 { /* WDOG1 */ Loading Loading @@ -191,10 +196,17 @@ i2c@83fc4000 { /* I2C2 */ status = "okay"; codec: sgtl5000@0a { sgtl5000: codec@0a { compatible = "fsl,sgtl5000"; reg = <0x0a>; clock-frequency = <26000000>; VDDA-supply = <&vdig_reg>; VDDIO-supply = <&vvideo_reg>; }; }; audmux@83fd0000 { status = "okay"; }; ethernet@83fec000 { Loading @@ -214,4 +226,18 @@ gpio-key,wakeup; }; }; sound { compatible = "fsl,imx51-babbage-sgtl5000", "fsl,imx-audio-sgtl5000"; model = "imx51-babbage-sgtl5000"; ssi-controller = <&ssi2>; audio-codec = <&sgtl5000>; audio-routing = "MIC_IN", "Mic Jack", "Mic Jack", "Mic Bias", "Headphone Jack", "HP_OUT"; mux-int-port = <2>; mux-ext-port = <3>; }; };
arch/arm/boot/dts/imx51.dtsi +33 −0 Original line number Diff line number Diff line Loading @@ -102,6 +102,15 @@ status = "disabled"; }; ssi2: ssi@70014000 { compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; reg = <0x70014000 0x4000>; interrupts = <30>; fsl,fifo-depth = <15>; fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */ status = "disabled"; }; esdhc@70020000 { /* ESDHC3 */ compatible = "fsl,imx51-esdhc"; reg = <0x70020000 0x4000>; Loading Loading @@ -235,6 +244,30 @@ status = "disabled"; }; ssi1: ssi@83fcc000 { compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; reg = <0x83fcc000 0x4000>; interrupts = <29>; fsl,fifo-depth = <15>; fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */ status = "disabled"; }; audmux@83fd0000 { compatible = "fsl,imx51-audmux", "fsl,imx31-audmux"; reg = <0x83fd0000 0x4000>; status = "disabled"; }; ssi3: ssi@83fe8000 { compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; reg = <0x83fe8000 0x4000>; interrupts = <96>; fsl,fifo-depth = <15>; fsl,ssi-dma-events = <47 46 37 35>; /* TX0 RX0 TX1 RX1 */ status = "disabled"; }; ethernet@83fec000 { compatible = "fsl,imx51-fec", "fsl,imx27-fec"; reg = <0x83fec000 0x4000>; Loading